T_TOBs_sorting.vhd File Reference

Top of Sorting_TOBs module for process FPGA. More...

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Entities
T_TOBs_sorting	entity
	Top of Sorting_TOBs module for process FPGA. More...
RTL	architecture
	Top of Sorting_TOBs module for process FPGA. More...

Detailed Description

Top of Sorting_TOBs module for process FPGA.

This module receives 7 x 32-bit Merged TOBs together with 7 valid signals in series, and sorts them into a 6 x 32-bit parallel word and 6 bit valid word to store in Circular DPRAM. The 7th TOB is ignored as a trailer is added to transfer the data to TOPO. In order to be able to read multi-slices, the TOBs and XTOBs must be converted into long parallel data words.

This module is only instantiated for Process FPGA 1 and 2, and is disabled for Process FPGA 3 and 4.

Only Process FPGA 1 and 2 transmit e/g and tau events to TOPO, and the off-line Readout, but Process FPGA 3 and 4 do not transmit to TOPO instead they send their TOBs to Process FPGA 1 and 2. Process FPGA 3 and 4 transmit XTOB only events to the Control FPGA.

The FSM then reads data from DPRAM into FIFO upon arrival of L1A The SIPO data is 209b = 7b TOB_BCN +4b error+6b valid +192b TOB data. The SIPO data of 209b is saved every BC tick to enable multi-slice readout.

Author

Saeed Taghavi

Definition in file T_TOBs_sorting.vhd.