eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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Instantiations | Processes | Signals
RTL Architecture Reference

Top of Sorting_TOBs module for process FPGA. More...

Processes

U6_TOB_clk280_proc  ( clk_in_280M_i )

Signals

clk_in_280M_i  STD_LOGIC
SIPO_T_TOB_out_i  STD_LOGIC_VECTOR ( 191 downto 0 )
SIPO_T_TOB_sync_out_i  STD_LOGIC
T_TOB_valid_out_i  STD_LOGIC_VECTOR ( 5 downto 0 )
DPR_T_TOBs_in_i  STD_LOGIC_VECTOR ( 208 downto 0 )
DPR_T_TOBs_out_i  STD_LOGIC_VECTOR ( 208 downto 0 )
rdout_T_TOB_209b_i  STD_LOGIC_VECTOR ( 208 downto 0 )
DPR_T_TOB_rd_addr_i  STD_LOGIC_VECTOR ( 8 downto 0 )
DPR_T_TOB_wr_addr_i  STD_LOGIC_VECTOR ( 8 downto 0 )
DRP_T_TOB_rd_en_i  std_logic
SIPO_T_TOB_sync_vec_i  STD_LOGIC_VECTOR ( 0 downto 0 )
FIFO_wr_en_i  std_logic
L1A_in_i  std_logic
FIFO_wr_en_tmp  std_logic
ALGO_TOB_BCN_out_i  std_logic_vector ( 6 downto 0 )
TOBs_FIFO_data_count_i  STD_LOGIC_VECTOR ( 8 downto 0 )
tied_to_vcc_i  std_logic
TOBs_data_valid_i  std_logic
TOBs_data_prog_full_i  std_logic
TOBs_data_full_i  std_logic
TOBs_data_empty_i  std_logic

Instantiations

u1_tobs_eg  SIPO_TOPO_TOBs_unit <Entity SIPO_TOPO_TOBs_unit>
u3_tobs_wr_fsm  fsm_TOB_wr_to_FIFO <Entity fsm_TOB_wr_to_FIFO>
u4_t_tob_drp  dpr_209b_512
u5_t_tobs_fifo  fifo_209b_512

Detailed Description

Top of Sorting_TOBs module for process FPGA.

This module receives 7 x 32-bit Merged TOBs together with 7 valid signals in series, and sorts them into a 6 x 32-bit parallel word and 6 bit valid word to store in Circular DPRAM. The 7th TOB is ignored as a trailer is added to transfer the data to TOPO. In order to be able to read multi-slices, the TOBs and XTOBs must be converted into long parallel data words.

This module is only instantiated for Process FPGA 1 and 2, and is disabled for Process FPGA 3 and 4.

Only Process FPGA 1 and 2 transmit e/g and tau events to TOPO, and the off-line Readout, but Process FPGA 3 and 4 do not transmit to TOPO instead they send their TOBs to Process FPGA 1 and 2. Process FPGA 3 and 4 transmit XTOB only events to the Control FPGA.

The FSM then reads data from DPRAM into FIFO upon arrival of L1A The SIPO data is 209b = 7b TOB_BCN +4b error+6b valid +192b TOB data. The SIPO data of 209b is saved every BC tick to enable multi-slice readout.

Author
Saeed Taghavi

Definition at line 85 of file T_TOBs_sorting.vhd.


The documentation for this class was generated from the following file: