SIPO_TOPO_TOBs_unit Entity Reference

SIPO Sorting TOBs for process FPGA. More...

Inheritance diagram for SIPO_TOPO_TOBs_unit:

Entities
Behavioral	architecture
	SIPO Sorting TOBs for process FPGA. More...

Libraries
IEEE
TOB_rdout_lib
Infrastructure_lib

Use Clauses
STD_LOGIC_1164
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
data_type_pkg	Package <data_type_pkg>

Ports
clk_in_280M	in	STD_LOGIC
		280Mhz input signal
TOBs_in	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		32b sorted TOB in - 7 x 32b words in series
TOBs_sync_in	in	STD_LOGIC
		TOB synch signal - indicating the start of the 7 TOB data words.
TOB_valid_flg_in	in	STD_LOGIC
		1b valid signal - 7 x 1b valid in series
ALGO_TOB_BCN_in	in	std_logic_vector ( 6 downto 0 )
		sorted TOB BCN with delay through ALGO/sorting block
TOPO_TOB_out	out	STD_LOGIC_VECTOR ( 191 downto 0 )
		6 * 32b sorted TOBs = 192b (ignore 7th TOB)
TOPO_TOB_sync_out	out	STD_LOGIC
		1b sorted TOBs synch signal output
TOPO_TOB_valid_out	out	STD_LOGIC_VECTOR ( 5 downto 0 )
		6b sorted TOBs valid (ignore 7th TOB)
ALGO_TOB_BCN_out	out	std_logic_vector ( 6 downto 0 )
		sorted TOB BCN with delay to match the delay on the TOBs through this block

Detailed Description

SIPO Sorting TOBs for process FPGA.

This file sorts the TOBs from 32b * 7 in series into one parallel word of 224b. The valid signals of all TOBs are paralled up into one 7b word.

Only 6 TOBs and 6 valid flags are stored, the 7th TOB data is ignored together with its valid flag.

Author

Saeed Taghavi

Definition at line 21 of file SIPO_TOPO_TOBs_unit.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/SIPO_TOPO_TOBs_unit.vhd