Behavioral Architecture Reference

SIPO Sorting TOBs for process FPGA. More...

Processes
U1_proc	( clk_in_280M )

Signals
reg_1_tmp	std_logic_vector ( 31 downto 0 )
reg_2_tmp	std_logic_vector ( 31 downto 0 )
reg_3_tmp	std_logic_vector ( 31 downto 0 )
reg_4_tmp	std_logic_vector ( 31 downto 0 )
reg_5_tmp	std_logic_vector ( 31 downto 0 )
reg_6_tmp	std_logic_vector ( 31 downto 0 )
sync_1_tmp	std_logic
sync_2_tmp	std_logic
sync_3_tmp	std_logic
sync_4_tmp	std_logic
sync_5_tmp	std_logic
sync_6_tmp	std_logic
wr_1_tmp	std_logic
wr_2_tmp	std_logic
wr_3_tmp	std_logic
wr_4_tmp	std_logic
wr_5_tmp	std_logic
wr_6_tmp	std_logic

Instantiations
u3_tob_bcn_delay	GeneralDelay <Entity GeneralDelay>

Detailed Description

SIPO Sorting TOBs for process FPGA.

This file sorts the TOBs from 32b * 7 in series into one parallel word of 224b. The valid signals of all TOBs are paralled up into one 7b word.

Only 6 TOBs and 6 valid flags are stored, the 7th TOB data is ignored together with its valid flag.

Author

Saeed Taghavi

Definition at line 45 of file SIPO_TOPO_TOBs_unit.vhd.

---

The documentation for this class was generated from the following file:

• Readout/src/SIPO_TOPO_TOBs_unit.vhd