SIPO_TOPO_TOBs_unit.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
library TOB_rdout_lib;
use TOB_rdout_lib.TOB_rdout_ip_pkg.ALL;
use TOB_rdout_lib.data_type_pkg.all;
 
library Infrastructure_lib;
 
entity SIPO_TOPO_TOBs_unit is
    Port ( 
        clk_in_280M          : in STD_LOGIC;
        TOBs_in              : in STD_LOGIC_VECTOR (31 downto 0);
        TOBs_sync_in         : in STD_LOGIC;
        TOB_valid_flg_in     : in STD_LOGIC;
        ALGO_TOB_BCN_in         : in std_logic_vector(6 downto 0);
        TOPO_TOB_out         : out STD_LOGIC_VECTOR (191 downto 0); 
        TOPO_TOB_sync_out    : out STD_LOGIC;
        TOPO_TOB_valid_out    : out STD_LOGIC_VECTOR (5 downto 0);
        ALGO_TOB_BCN_out      : out std_logic_vector(6 downto 0)
        );
end SIPO_TOPO_TOBs_unit;
 
architecture Behavioral of SIPO_TOPO_TOBs_unit is
 
    signal  reg_1_tmp        : std_logic_vector(31 downto 0);   -- 32b sorted TOB
    signal  reg_2_tmp        : std_logic_vector(31 downto 0);
    signal  reg_3_tmp        : std_logic_vector(31 downto 0);
    signal  reg_4_tmp        : std_logic_vector(31 downto 0);
    signal  reg_5_tmp        : std_logic_vector(31 downto 0);
    signal  reg_6_tmp        : std_logic_vector(31 downto 0);
    
    signal  sync_1_tmp       : std_logic;
    signal  sync_2_tmp       : std_logic;
    signal  sync_3_tmp       : std_logic;
    signal  sync_4_tmp       : std_logic;
    signal  sync_5_tmp       : std_logic;
    signal  sync_6_tmp       : std_logic;
 
    signal  wr_1_tmp       : std_logic;
    signal  wr_2_tmp       : std_logic;
    signal  wr_3_tmp       : std_logic;
    signal  wr_4_tmp       : std_logic;
    signal  wr_5_tmp       : std_logic;
    signal  wr_6_tmp       : std_logic;
    
begin
 
-- This module delays the BCN to match the delay of the TOBs Data through this block.
 
U3_TOB_BCN_Delay : entity Infrastructure_lib.GeneralDelay
    generic map (
      delay => 5,   --generates delay of 5 + 1 clocks
      size  => 7)
    port map (
      clk      => clk_in_280M,
      data_in  => ALGO_TOB_BCN_in,
      data_out => ALGO_TOB_BCN_out);
 
U1_proc : process (clk_in_280M)
    begin
        if(clk_in_280M'event and clk_in_280M = '1') then
--            sync_7_tmp <= TOBs_sync_in;       -- register input sync data
            sync_6_tmp <= TOBs_sync_in;      
            sync_5_tmp <= sync_6_tmp;      
            sync_4_tmp <= sync_5_tmp;      
            sync_3_tmp <= sync_4_tmp;
            sync_2_tmp <= sync_3_tmp;
            sync_1_tmp <= sync_2_tmp;
                  
--            reg_7_tmp  <= TOBs_in ;         -- register input data 
            reg_6_tmp <= TOBs_in;       
            reg_5_tmp <= reg_6_tmp;       
            reg_4_tmp <= reg_5_tmp;       
            reg_3_tmp <= reg_4_tmp;       
            reg_2_tmp <= reg_3_tmp;       
            reg_1_tmp <= reg_2_tmp;       
    
--            wr_7_tmp  <= TOB_valid_flg_in ;         -- register input data valid
            wr_6_tmp <= TOB_valid_flg_in;       
            wr_5_tmp <= wr_6_tmp;       
            wr_4_tmp <= wr_5_tmp;       
            wr_3_tmp <= wr_4_tmp;       
            wr_2_tmp <= wr_3_tmp;       
            wr_1_tmp <= wr_2_tmp;       
    
--            link_err_4b_out   <= link_err_4b_in;
            
        end if;
    end process U1_proc;
    
    -- need only 6 TOBs, ignore 7th TOB value
    TOPO_TOB_out        <= reg_6_tmp & reg_5_tmp & reg_4_tmp & reg_3_tmp & reg_2_tmp & reg_1_tmp;
    TOPO_TOB_valid_out  <= wr_6_tmp & wr_5_tmp & wr_4_tmp & wr_3_tmp & wr_2_tmp & wr_1_tmp;
    TOPO_TOB_sync_out   <= sync_1_tmp;
 
--U1_ila_TOB_sorting : ila_ipbus_fabric_rd_wr
--PORT MAP (
--  clk    => clk_in_280M ,
--  probe0(31 downto 0) => TOBs_in ,     -- 36b 
--  probe0(35 downto 32) => (others => '0' ) ,     -- 36b 
--  probe1 => (others => '0' ) ,         -- 36b  
--  probe2(0) => TOBs_sync_in ,  -- 1b 
--  probe3(0) => TOB_valid_flg_in,     -- 1b
--  probe4 => (others => '0' ),    -- 1b
--  probe5(31 downto 0)  => reg_6_tmp,    --36b 
--  probe5(35 downto 32) => (others => '0' ),    --36b 
--    probe6(5 downto 0)   => TOPO_TOB_valid_out,    -- 36b
--    probe6(35 downto 6)  => (others => '0' ),    -- 36b
--    probe7 => (others => '0' ),   -- 1b
--  probe8 => (others => '0' )  ,   -- 1b
--    probe9(0) => TOPO_TOB_sync_out    -- 1b
--);
 
end Behavioral;