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eFEX firmware
1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards
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SIPO Sorting TOBs for process FPGA. More...
Go to the source code of this file.
Entities | |
| SIPO_TOPO_TOBs_unit | entity |
| SIPO Sorting TOBs for process FPGA. More... | |
| Behavioral | architecture |
| SIPO Sorting TOBs for process FPGA. More... | |
SIPO Sorting TOBs for process FPGA.
This file sorts the TOBs from 32b * 7 in series into one parallel word of 224b. The valid signals of all TOBs are paralled up into one 7b word.
Only 6 TOBs and 6 valid flags are stored, the 7th TOB data is ignored together with its valid flag.
Definition in file SIPO_TOPO_TOBs_unit.vhd.
1.9.1