TOBs_rdout Entity Reference

Merged Sorted TOB and Local XTOB Readout Logic for process FPGA. More...

Inheritance diagram for TOBs_rdout:

Entities
RTL	architecture
	Merged Sorted TOB and Local XTOB Readout Logic for process FPGA. More...

Libraries
ieee
ipbus_lib
UNISIM
UNIMACRO
TOB_rdout_lib
algolib

Use Clauses
std_logic_1164
numeric_std
ipbus
vcomponents
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
data_type_pkg	Package <data_type_pkg>
AlgoDataTypes	Package <AlgoDataTypes>

Generics
FPGA_NUMBER	integer := 1
	Integer used to distinguish different FPGAs having a slightly different firmware.

Ports
RST	in	std_logic
hw_addr	in	STD_LOGIC_VECTOR ( 1 downto 0 )
		FPGA Hardware Address.
RST_spy_mem_wr_addr	in	std_logic
		spy memory write address counter reset Pulse by software command
TOB_FIFO_sw_rst	in	std_logic
		TOB Readout FIFO reset Pulse by software command.
XTOB_eg_512b_in	in	AlgoXOutput
		array 8 x 64b words XTOB e/g
XTOB_eg_Valid_flg_in	in	STD_LOGIC_VECTOR ( 7 downto 0 )
		8b XTOB e/g has valid data
XTOB_eg_sync_in	in	STD_LOGIC
		XTOB e/g sync signal.
XTOB_tau_512b_in	in	AlgoXOutput
		array 8 x 64b words XTOB tau
XTOB_tau_Valid_flg_in	in	STD_LOGIC_VECTOR ( 7 downto 0 )
		8b XTOB tau has valid data
XTOB_tau_sync_in	in	STD_LOGIC
		XTOB tau sync signal.
OUT_XTOB_BCN	in	std_logic_vector ( 6 downto 0 )
		XTOB BCN with delay through ALGO/sorting block.
TOBs_32b_in	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Sorted TOB data 32b * 7 in series, F1 reads e/g TOBs and F2 reads tau TOBs. Same firmware in both FPGAs, use hw addr to differentiate.
TOBs_sync_in	in	STD_LOGIC
		sorted TOB start signal
TOBs_valid_flg_in	in	STD_LOGIC
		sorted TOB write signal
OUT_TOB_BCN	in	std_logic_vector ( 6 downto 0 )
		sorted TOB BCN with delay through ALGO/sorting block
TOB_type_in	in	STD_LOGIC
		TOB Type 0 = e/g for pFPGA U1, TOB Type U1 = tau for pFPGA 2, also Zero for U3 & U4.
read_on_err_in	in	STD_LOGIC
		Read RAW data on error flag.
clk_40M_in	in	STD_LOGIC
		40MHz clock input signal
clk_200M_in	in	STD_LOGIC
		200Mhz input signal
clk_280M_in	in	STD_LOGIC
		280MHz clock input signal
TOB_TXOUTCLK	in	STD_LOGIC
		280Mhz clk to read data into MGT
shelf_number	in	STD_LOGIC_VECTOR ( 3 downto 0 )
		shelf number input
efex_slot_num	in	STD_LOGIC_VECTOR ( 3 downto 0 )
		eFEX slot number input
L1A_in	in	STD_LOGIC
		L1A signal input.
BCN_ID_in	in	STD_LOGIC_VECTOR ( 11 downto 0 )
		BC Counter.
L1A_ID_in	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		8b Extended L1A ID & 24b LIA_ID of the L1A Counter
TOB_ready_in	in	std_logic
		Ready signal from control FPGA to receive TOBs data.
TOB_out_to_MGT_is_char	out	STD_LOGIC
		data is char to MGT
TOB_out_to_MGT	out	STD_LOGIC_VECTOR ( 31 downto 0 )
		Event TOBs 32b out to MGT.
L1A_ID_Event_out	out	STD_LOGIC_VECTOR ( 31 downto 0 )
		8b Ext L1A ID from TTC input + 24b L1A ID of counter from TTC FIFO - inserted in the event header
pre_ld_TOB_wr_addr	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		latency pre load for TOB DRP wr address
pre_ld_eg_XTOB_wr_addr	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		latency pre load for e/g XTOB DRP wr address
pre_ld_tau_XTOB_wr_addr	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		latency pre load for tau XTOB DRP wr address
cntr_load_en	in	STD_LOGIC
		latency pre-load enable for DRPAM write address
DPR_locations_to_rd	in	STD_LOGIC_VECTOR ( 2 downto 0 )
		number of slices (DRP locations) to read 1 or 2 or 3
trigger_slice_in	in	STD_LOGIC_VECTOR ( 3 downto 0 )
		Trigger slice number - on L1A.
TOB_data_FIFO_flags	out	STD_LOGIC_VECTOR ( 31 downto 0 )
		TOB data block FIFO flags.
XTOB_eg_FIFO_rd_data_count	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		occupancy counter of e/g XTOB FIFO - read clock
XTOB_eg_FIFO_pFULL_THRESH_assert	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		e/g XTOB FIFO prog FULL threshold assert
XTOB_eg_FIFO_pFULL_THRESH_negate	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		e/g XTOB FIFO prog FULL threshold de-assert
XTOB_tau_FIFO_rd_data_count	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		tau XTOBs FIFO occupancy data count - read clock
XTOB_tau_FIFO_pFULL_THRESH_assert	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		tau XTOB FIFO prog FULL threshold assert
XTOB_tau_FIFO_pFULL_THRESH_negate	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		tau XTOB FIFO prog FULL threshold de-assert
T_TOB_FIFO_data_count	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		sorted TOBs FIFO occupancy data count
T_TOBs_FIFO_pFULL_THRESH_assert	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		sorted TOBs FIFO prog FULL threshold assert
T_TOBs_FIFO_pFULL_THRESH_negate	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		sorted TOBs FIFO prog FULL threshold de-assert
tob_busy_thresh_assert	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		sorted TOB BUSY flag threshold assert
tob_busy_thresh_negate	in	STD_LOGIC_VECTOR ( 8 downto 0 )
		sorted TOB BUSY flag threshold de-assert
BCN_FIFO_pFULL_THRESH_assert	in	std_logic_vector ( 8 downto 0 )
		BCN FIFO partial full flag assert threshold.
BCN_FIFO_pFULL_THRESH_negate	in	std_logic_vector ( 8 downto 0 )
		BCN FIFO partial full flag negate threshold.
BCN_FIFO_TOB_rd_data_count	out	STD_LOGIC_VECTOR ( 8 downto 0 )
		BCN & L1A FIFO occupancy for TOB Readout.
Link_output_FIFO_pFULL_THRESH_assert	in	STD_LOGIC_VECTOR ( 12 downto 0 )
		Link output FIFO (before MGT) partial full flag assert threshold.
Link_output_FIFO_pFULL_THRESH_negate	in	STD_LOGIC_VECTOR ( 12 downto 0 )
		Link output FIFO (before MGT) partial full flag negate threshold.
Link_output_FIFO_rd_data_count	out	STD_LOGIC_VECTOR ( 12 downto 0 )
		Link output FIFO (before MGT) occupancy read data count.
SPY_TOB_mem_wr_addr	out	STD_LOGIC_VECTOR ( 10 downto 0 )
		TOB/XTOB Readout SPY Memory register (read only)
ipb_clk	in	std_logic
		ipb_clk signal is input from master to slaves
ipbus_out_tob_dpram	out	ipb_rbus
		IPBus signal coming from RAW SPY DPRAM to IPBus.
ipbus_in_tob_dpram	in	ipb_wbus
		IPBus signal going to RAW SPY DPRAM.
busy_tob	out	std_logic
		tob data busy out to control FPGA
sync_280m_out	out	STD_LOGIC
		280MHz synch signal output
tob_double_word_en	out	STD_LOGIC
		TOB double word enable to increments double word counter,.
tob_fsm_monitor	out	std_logic_vector ( 39 downto 0 )
		Monitor TOB Readout state machines.

Detailed Description

Merged Sorted TOB and Local XTOB Readout Logic for process FPGA.

This module received Merged Sorted TOB and Local XTOB data and produces events of 32b words for transmission to control FPGA

Global Sorted TOBs and Local XTOB Readout Logic Block Diagram

This module is only instanstiated for Process FPGA 1 and 2, and is disabled for Process FPGA 3 and 4.

Different TOB/XTOB data event are generated depending on FPGA Number, buffer levels and control settings.

The Merging FPGAs generate TOB/XTOB data events which consist of maximum 20 tau XTOBs, 20 e/g XTOBs and up to 6 TOBs.

The Non-Merging FPGAs generate XTOB data events which consist of maximum 20 tau XTOBs, 20 e/g XTOBs and do not include Merged TOBs.

• Process FPGA 1 is a merging FPGAs, receive Merged e/g TOBs from the other 3 FPGA. Process FPGA 1 creates an event consisting of locally generated e/g and tau XTOBs, together with Merged e/g TOBs..
• Process FPGA 2 is a merging FPGAs, receive Merged tau TOBs from the other 3 FPGA. Process FPGA 2 creates an event consisting of locally generated e/g and tau XTOBs, together with Merged tau TOBs..
• Process FPGA 3 and 4 are non-merging FPGAs, so do not receive any TOB data from other FPGAs. Process FPGA 3 and 4 create event consisting of locally generated e/g and tau XTOBs, but do not include and Merged TOBs..

1. Readout operation for Process FPGAs 1 & 2, create Events which consists of only Valid XTOB/TOBs.
   • TOB & XTOB Event in Normal Operation:
     • Read 1 Slice - Takes 179 ticks of 280MHz clock to create one TOB & XTOB Event with 1 Slice Readout.
   • TOB & XTOB Event in Normal Operation:
     • Read 2 Slice - Takes 352 ticks of 280MHz clock to create one TOB & XTOB Event with 2 Slice Readout.
   • TOB & XTOB Event in Normal Operation:
     • Read 3 Slice - Takes 524 ticks of 280MHz clock to create one TOB & XTOB Event with 3 Slice Readout.
   • TOB & XTOB Event in Normal Operation:
     • Read 4 Slice - Takes 697 ticks of 280MHz clock to create one TOB & XTOB Event with 4 Slice Readout.
   • TOB & XTOB Event in SAFE Mode Operation:
     • Read 0 Slices - Takes 8 ticks of 280MHz clock to create one SAFE Mode TOB & XTOB Event.
2. Readout operation for Process FPGAs 3 & 4, create Events which consists of only Valid e/g and tau XTOBs..
   • XTOB Event in Normal Operation: Read 1 Slice - Takes 171 ticks of 280MHz clock to create one XTOB Event with 1 Slice Readout.
   • XTOB Event in Normal Operation: Read 2 Slice - Takes 344 ticks of 280MHz clock to create one XTOB Event with 2 Slice Readout.
   • XTOB Event in Normal Operation: Read 3 Slice - Takes 516 ticks of 280MHz clock to create one XTOB Event with 3 Slice Readout.
   • XTOB Event in Normal Operation: Read 4 Slice - Takes 691 ticks of 280MHz clock to create one XTOB Event with 4 Slice Readout.
   • XTOB Event in SAFE Mode Operation: Read 0 Slice - Takes 8 ticks of 280MHz clock to create one SAFE Mode XTOB Event.

Sequence of Buffers occupancy levels:

1. When the Ready signal from Control FPGA is removed, complete TOB/XTOB Events are stored in TOB/XTOB Link Output FIFO.
   • When the occupancy of TOB Link Output FIFO reaches its prog FULL occupancy level, then the construction of TOB/XTOB Events are paused.
   • Enough headroom must be assigned in Link Output FIFO to be able to store TOB/XTOB Events under Safe Mode operation.
2. At this point, TOB/XTOB data are still transferred from Circular DPRAM into de-randomisation TOB/XTOB Data FIFO.
   • When the occupancy of de-randomisation TOB/XTOB Data FIFO or TTC FIFO reaches its prog FULL occupancy level,
   • A Safe Mode Flag is set which is used to create Safe Mode TOB/XTOB events and empty the TOB/XTOB Data FIFO & TTC FIFO.
   • These Safe Mode events consists of 2 Header words, and one Trailer word.
   • The payload consists of two words, a ZERO word together with a sub-trailer word for the slice.
   • Multi-slice readout contains a number of these double words, equal to the number of slices to be readout.
   • A BUSY request must be sent to HUB/ROD to reduce L1A rates at this time.
   • In Safe Mode, all buffers, except TOB/XTOB Link Output FIFO, are flushed, and very small TOB/XTOB Events are generated and stored in Link Output FIFO.

Under Safe Mode operation if the occupancy of TTC FIFO or TOB/XTOB Data FIFO, reaches its FULL occupancy level, then the system synchronisation is lost.

The output of TOB Readout is:

• 32-bit data word
• 1-bit data is CHAR
• 1-bit valid which is the write enable to Link Output FIFO

Header Word 1:

• TOBs_out_i(31:24) = TOB BCN
• TOBs_out_i(23:20) = XTOB BCN
• TOBs_out_i(19:8) = Local (internal) BCN
• TOBs_out_i(7:0) = ch_sop = X"3C" (K28.1)

Header Word 2:

• TOBs_out_i(31:24) = Extended L1_ID
• TOBs_out_i(23:0) = Level 1 ID

Trailer Word 1: Slice Trailer

• TOBs_out_i(31) = ZERO
• TOBs_out_i(30) = link_err_flg_in_i
• TOBs_out_i(29:28) = FPGA_mapping
• TOBs_out_i(27) = safe mode
• TOBs_out_i(26:24) = slice number transmitted
• TOBs_out_i(23:18) = XTOB counter tau
• TOBs_out_i(17:12) = XTOB counter e/g
• TOBs_out_i(11:9) = TOB counter
• TOBs_out_i(8) = TOB type in
• TOBs_out_i(7:0) = slice_end = X"5C" (K28.2)

Trailer Word 2: Event Trailer

• TOBs_out_i(31) = safe mode
• TOBs_out_i(30:27) = ZERO
• TOBs_out_i(26:24) = DPR_locations_to_rd (number of slices to read)
• TOBs_out_i(23:20) = trigger slice number
• TOBs_out_i(19:8) = TOB payload counter
• TOBs_out_i(7:0) = ch_eop = X"DC" (K28.6)

CHAR constants are defined in data_type_pkg.vhd

• for reference only
  • constant ch_idle : std_logic_vector(7 downto 0) := X"BC" ; – idle char is K28.5
  • constant ch_sop1 : std_logic_vector(7 downto 0) := X"3C" ; – TOB/XTOB star of packet char is K28.1
  • constant ch_sop2 : std_logic_vector(7 downto 0) := X"7C" ; – CALO DATA start of packet char is K28.3
  • constant ch_eop : std_logic_vector(7 downto 0) := X"DC" ; – end of packet char is K28.6
  • constant slice_end : std_logic_vector(7 downto 0) := X"5C" ; – end of TOB slice char is K28.2
  • constant tx_pause : std_logic_vector(7 downto 0) := X"1C" ; – Tx Data pause is K28.0

TRIGGER SLICE:

• identifies the slice number on L1A, as a number between 0 to 4
• TOB packet header word gets TOB/XTOB BCN from TOB/XTOB data, but internal BCN from L1A_TOB FIFO
• L1A_TOB BCN is always the BCN on L1A, but TOB/XTOB BCN changes depending on Trigger Slice value

07/03/2024 Due to intermitent read error of L1_ID, and further investigations, we found that the input to L1_ID & BNCN FIFO has crossed clock domain from 40MHz to 280MHz. To rule out this may be the cause of error, it was decided to remove read_on_err_in signal from the slice trailer and set it to ZERO.

Author

Saeed Taghavi

Definition at line 149 of file TOBs_rdout.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/TOBs_rdout.vhd