RAW_data_rdout.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library ipbus_lib;
use ipbus_lib.ipbus.all;
 
Library UNISIM;
use UNISIM.vcomponents.all;
 
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
 
library TOB_rdout_lib;
use TOB_rdout_lib.data_type_pkg.all;
use TOB_rdout_lib.TOB_rdout_ip_pkg.all;
 
entity RAW_data_rdout is
  generic
    (
      FPGA_NUMBER : integer := 1
      );
  port (
    RST                                      : in  std_logic;
    hw_addr                                  : in  std_logic_vector(1 downto 0);
    RST_spy_mem_wr_addr                      : in  std_logic;
    RAW_FIFO_sw_rst                          : in  std_logic;
    RAW_data_in                              : in  RAW_data_227_type;
    clk_40M_rdout                            : in  std_logic;
    clk_280M_in                              : in  std_logic;
    clk_load_in                              : in  std_logic;
    ipb_clk                                  : in  std_logic;
    RAW_ready_in                              : in  std_logic;
    RAW_TXOUTCLK                             : in  std_logic;
    L1A_in                                   : in  std_logic;
    BCN_ID_in                                : in  std_logic_vector (11 downto 0);
    L1A_ID_in                                : in  std_logic_vector (31 downto 0);
    raw_rd_all_in                            : in  std_logic;
    pre_ld_wr_addr                           : in  std_logic_vector (9 downto 0);
    RAW_FIFO_FULL_THRESH_ASSERT              : in  std_logic_vector (8 downto 0);
    RAW_FIFO_FULL_THRESH_NEGATE              : in  std_logic_vector (8 downto 0);
    RAW_FIFO_data_count                      : out std_logic_vector(8 downto 0);
    raw_busy_thresh_assert  : in  STD_LOGIC_VECTOR (8 downto 0);    -- TOBs FIFO
    raw_busy_thresh_negate  : in  STD_LOGIC_VECTOR (8 downto 0);    -- TOBs FIFO
    cntr_load_en                             : in  std_logic;
    RAW_data_FIFO_flags                      : out std_logic_vector (31 downto 0);
    RAW_out_to_MGT_is_char                   : out std_logic;
    RAW_data_out                             : out std_logic_vector (31 downto 0);  -- TOBs 32b out to MGT
    mgt_enable_in                            : in STD_LOGIC_VECTOR (48 downto 0) ;
    frame_count                              : out std_logic_vector (31 downto 0);
    read_on_err_out                          : out  STD_LOGIC;     
    TTC_read_all_in                          : in  std_logic;
    RAW_FIFO_pFULL_THRESH_ASSERT             : in  std_logic_vector (8 downto 0);  -- MGT_FIFO
    RAW_FIFO_pFULL_THRESH_NEGATE             : in  std_logic_vector (8 downto 0);  -- MGT_FIFO
    BCN_FIFO_pFULL_THRESH_assert             : in  std_logic_vector(8 downto 0);
    BCN_FIFO_pFULL_THRESH_negate             : in  std_logic_vector(8 downto 0);
    BCN_FIFO_RAW_rd_data_count         : out STD_LOGIC_VECTOR (8 downto 0);   -- occupancy of BCN & L1A FIFO for RAW Readout
    Link_output_FIFO_RAW_pfull_thresh_assert : in  std_logic_vector (12 downto 0);  -- Link_output_FIFO
    Link_output_FIFO_RAW_pfull_thresh_negate : in  std_logic_vector (12 downto 0);  -- Link_output_FIFO
    Link_output_FIFO_RAW_rd_data_count       : out std_logic_vector (12 downto 0);  -- occupancy of RAW output link MGT FIFO
    SPY_mem_wr_addr                          : out std_logic_vector (10 downto 0);  -- SPY memory wr_addr (read only)
    ipbus_out_raw_dpram                      : out ipb_rbus;
    ipbus_in_raw_dpram                       : in  ipb_wbus;
    link_error_flags                         : out std_logic_vector (53 downto 0);
    busy_raw          : out std_logic;  
    raw_fsm_monitor   : out std_logic_vector (31 downto 0)  
    );
end RAW_data_rdout;
 
architecture RTL of RAW_data_rdout is
 
--***********************************Parameter Declarations********************
  constant chan_no : integer := 49;
--************************** Register Declarations ****************************
 
  signal DPR_rd_addr_i      : std_logic_vector (9 downto 0);
  signal DPR_wr_addr_i      : std_logic_vector (9 downto 0);
  signal DPR_rd_addr_i_1dly : std_logic_vector (9 downto 0);
  signal DPR_wr_addr_i_1dly : std_logic_vector (9 downto 0);
 
  signal FIFO_RAW_Data_dout_i      : DPR_RAW_out_36_type;  -- array 49 of 36b = err + data
  signal FIFO_RAW_Data_dout_i_1dly : DPR_RAW_out_36_type;  -- array 49 of 36b = err + data
 
  signal link_error_flags_tmp     : link_error_type;  -- array 49 x 4 bit per link
  signal link_err_4b_in_i         : std_logic_vector (3 downto 0);  -- place holder for overall error flags of all optical link inputs.
  signal channel_error_49b_i      : std_logic_vector (48 downto 0);
  signal link_error_flags_54b_i   : std_logic_vector (53 downto 0);
  signal FIFO_error_flags_54b_i   : std_logic_vector (53 downto 0);
  signal req_err_rd_raw_i         : std_logic := '0';  -- flag to request RAW data read out upon error
  signal FIFO_error_flags_valid_i : std_logic;
 
 
  signal PISO_data_out_i    : DPR_RAW_out_36_type;  -- array 49 of 36b = err + data
  signal DPR_RAW_out_i      : DPR_RAW_out_36_type;  -- array 49 of 36b = err + data
  signal DPR_RAW_out_i_1dly : DPR_RAW_out_36_type;  -- array 49 of 36b = err + data
 
  signal RST_i                 : std_logic;
  signal Read_all_i            : std_logic;  -- privilege read All Flag
  signal RAW_FIFO_sw_rst_i     : std_logic;
  signal clk_in_280M_i         : std_logic;
  signal PISO_sync_out_i       : t_49_arr_1b;  -- 49 sync signals for 49 links
  signal PISO_data_out_valid_i : t_49_arr_1b;  -- 49 sync signals for 49 links
 
  signal L1A_in_i, L1A_in_1dly : std_logic;
  signal L1A_in_a              : std_logic;
  signal L1A_in_b              : std_logic;
  signal DRP_rd_en_i           : std_logic;
  signal DRP_rd_en_i_1dly      : std_logic;
 
  signal FIFO_wr_en_i      : std_logic;
  signal FIFO_wr_en_i_1dly : std_logic;
  signal FIFO_wr_en_i_2dly : t_49_arr_1b;
  signal FIFO_rd_en_i      : t_49_arr_1b;
 
  signal BCN_FIFO_rd_en_i  : std_logic;
  signal en_error_valid_i                                              : std_logic;
  signal en_error_valid_1dly, en_error_valid_2dly, en_error_valid_3dly : std_logic;
  signal en_error_valid_4dly                                           : std_logic;
 
  signal link_err_FIFO_empty_i : std_logic;
  signal BCN_FIFO_full_i       : std_logic;
  signal BCN_FIFO_empty_i      : std_logic;
  signal BCN_FIFO_valid_i      : std_logic;
  signal BCN_FIFO_prog_full_i  : std_logic;
  signal BCN_FIFO_Data_in_i    : std_logic_vector(46 downto 0);
  signal BCN_FIFO_Data_out_i   : std_logic_vector(46 downto 0);
 
  signal BCN_FIFO_pFULL_THRESH_assert_i : std_logic_vector(8 downto 0);
  signal BCN_FIFO_pFULL_THRESH_negate_i : std_logic_vector(8 downto 0);
 
  signal Link_output_FIFO_RAW_pfull_thresh_assert_i : std_logic_vector(12 downto 0);
  signal Link_output_FIFO_RAW_pfull_thresh_negate_i : std_logic_vector(12 downto 0);
 
  signal RAW_data_FIFO_pFULL_THRESH_assert_i : std_logic_vector(8 downto 0);
  signal RAW_data_FIFO_pFULL_THRESH_negate_i : std_logic_vector(8 downto 0);
  signal RAW_data_FIFO_count_i               : std_logic_vector(8 downto 0);
  signal FIFO_RAW_Data_prog_full_i           : std_logic_vector(48 downto 0);
  signal FIFO_RAW_Data_full_i                : std_logic;  -- RAW FIFO full flag based on occupancy
  signal FIFO_RAW_Data_empty_i               : std_logic_vector(48 downto 0);
  signal FIFO_RAW_Data_valid_i               : t_49_arr_1b;  -- 49 sync signals for 49 links
  signal FIFO_RAW_Data_valid_i_1dly          : t_49_arr_1b;  -- 49 sync signals for 49 links
  signal sync_280m_i                         : t_49_arr_1b;  -- 49 sync signals for 49 links
 
  signal FIFO_RAW_Data_prog_full_tmp  :  std_logic; 
  signal FIFO_RAW_Data_empty_tmp      :  std_logic; 
 
  signal frame_cntr_dec_en_i                                                : std_logic;
  signal frame_counter_dec_en_i                                             : std_logic;
  signal op_fifo_frame_count_i                                              : std_logic_vector (11 downto 0);  -- Frame counter
  signal frame_cntr_en_i, frame_cntr_en_ii                                  : std_logic;
  signal RAW_out_valid_i, RAW_data_out_valid_i, RAW_out_valid_1dly          : std_logic;
  signal RAW_out_char_MGT_i                                                 : std_logic;
  signal RAW_data_out_MGT_i                                                 : std_logic_vector(31 downto 0);
  signal RAW_out_is_char_i, RAW_out_to_MGT_is_char_i, RAW_out_char_MGT_1dly : std_logic;
  signal RAW_out_i, q_int, RAW_data_out_i, RAW_data_out_1dly                : std_logic_vector(31 downto 0);
 
  signal FIFO_RAW_in_i : std_logic_vector(32 downto 0);
 
  signal Link_output_FIFO_RAW_out_i   : std_logic_vector (32 downto 0);  -- TOBs 33b out to MGT
  signal Link_output_FIFO_rd_en_i     : std_logic;
  signal Link_output_FIFO_RAW_valid_i : std_logic;
 
  signal Link_output_FIFO_full_i      : std_logic;
  signal Link_output_FIFO_empty_i     : std_logic;
  signal Link_output_FIFO_prog_full_i : std_logic;
 
  signal reg1, reg2      : std_logic := '0';
  signal RAW_safe_mode_i : std_logic;
  signal RAW_busy_assert_i : std_logic;
  signal RAW_ready_in_i   : std_logic;
 
  signal enable_raw_spy_mem_wr      : std_logic;
  signal SPY_mem_wr_addr_i          : std_logic_vector (10 downto 0);
  signal SPY_mem_wr_addr_en_i       : std_logic;
  signal SPY_mem_rd_data_i          : std_logic_vector (35 downto 0);
  signal RAW_data_FIFO_flags_i      : std_logic_vector (31 downto 0);
  signal delayed_crc_error_i        : std_logic_vector (48 downto 0);
  signal busy_raw_i                 :  std_logic; -- raw data busy
  signal SPY_mem_wr_addr_tc_i       :  std_logic; -- spy ram address terminal count
   
  -- this is the array of 49 x 32b
  type DPRAM_addr_1b_type is array ((chan_no - 1) downto 0) of std_logic_vector (0 downto 0);
  type RAW_fifo_d_count_type is array ((chan_no - 1) downto 0) of std_logic_vector (8 downto 0);
  signal data_count_i : RAW_fifo_d_count_type;
 
  signal LO_FIFO_RAW_rd_data_count_i  : std_logic_vector (12 downto 0);  -- occupancy of RAW output link MGT FIFO - rd
  signal LO_FIFO_RAW_wr_data_count_i  : std_logic_vector (12 downto 0);  -- occupancy of RAW output link MGT FIFO - wr
  signal RAW_data_in_1dly                     : RAW_data_227_type;  -- array 49 x 227b input frames
  signal raw_data_dpram_fsm_i, raw_data_mux_fsm_i, raw_data_mgt_fsm_i : std_logic_vector (7 downto 0);
 
--  ####### Attributes  ########
  attribute mark_debug : string;
  attribute keep       : string;
  attribute max_fanout : integer;
 
  attribute keep of RAW_out_valid_i       : signal is "true";
  attribute max_fanout of RAW_out_valid_i : signal is 100;
 
  attribute keep of FIFO_RAW_in_i : signal is "true";
 
  attribute keep of RAW_FIFO_sw_rst_i       : signal is "true";
  attribute max_fanout of RAW_FIFO_sw_rst_i : signal is 100;
 
  attribute keep of FIFO_wr_en_i_2dly       : signal is "true";
  attribute max_fanout of FIFO_wr_en_i_2dly : signal is 30;
 
  attribute keep of FIFO_rd_en_i       : signal is "true";
  attribute max_fanout of FIFO_rd_en_i : signal is 30;
 
  attribute keep of FIFO_wr_en_i       : signal is "true";
  attribute max_fanout of FIFO_wr_en_i : signal is 30;
 
  attribute keep of SPY_mem_wr_addr_en_i       : signal is "true";
  attribute max_fanout of SPY_mem_wr_addr_en_i : signal is 30;
 
  attribute keep of BCN_FIFO_empty_i                   : signal is "true";
  attribute max_fanout of BCN_FIFO_empty_i             : signal is 30;
  attribute keep of Link_output_FIFO_prog_full_i       : signal is "true";
  attribute max_fanout of Link_output_FIFO_prog_full_i : signal is 30;  
  attribute keep of FIFO_RAW_Data_prog_full_i       : signal is "true";
  attribute max_fanout of FIFO_RAW_Data_prog_full_i : signal is 30;  
 
  attribute keep of DPR_wr_addr_i_1dly       : signal is "true";
  attribute max_fanout of DPR_wr_addr_i_1dly : signal is 30;  
 
  attribute keep of RAW_data_out_1dly    : signal is "true";
  attribute keep of RAW_out_valid_1dly   : signal is "true";
  attribute keep of RAW_data_out_MGT_i   : signal is "true";
  attribute keep of RAW_out_char_MGT_i   : signal is "true";
  attribute keep of RAW_data_out_i       : signal is "true";
  attribute keep of RAW_data_out_valid_i : signal is "true";
  attribute keep of BCN_FIFO_Data_in_i   : signal is "true";
  attribute keep of RAW_data_in          : signal is "true";
  attribute keep of RAW_data_in_1dly     : signal is "true";
  attribute keep of PISO_data_out_i      : signal is "true";
  attribute keep of FIFO_RAW_Data_dout_i : signal is "true";
  attribute keep of delayed_crc_error_i  : signal is "true";
--   #######################################
 
begin
 
  clk_in_280M_i <= clk_280M_in;
 
  L1A_in_i <= L1A_in;
  RST_i    <= RST;                      -- from 40MHz MMCM lock signal
 
  RAW_FIFO_sw_rst_i <= RST_i or RAW_FIFO_sw_rst;  -- rst by s/w or RST
  RAW_data_FIFO_pFULL_THRESH_assert_i        <= RAW_FIFO_pFULL_THRESH_ASSERT;
  RAW_data_FIFO_pFULL_THRESH_negate_i        <= RAW_FIFO_pFULL_THRESH_NEGATE;
  BCN_FIFO_pFULL_THRESH_assert_i             <= BCN_FIFO_pFULL_THRESH_assert;
  BCN_FIFO_pFULL_THRESH_negate_i             <= BCN_FIFO_pFULL_THRESH_negate;
  Link_output_FIFO_RAW_pfull_thresh_assert_i <= Link_output_FIFO_RAW_pfull_thresh_assert;
  Link_output_FIFO_RAW_pfull_thresh_negate_i <= Link_output_FIFO_RAW_pfull_thresh_negate;
 
  frame_count     <= X"00000" & op_fifo_frame_count_i;
  SPY_mem_wr_addr <= SPY_mem_wr_addr_i;
 
  RAW_data_out           <= RAW_data_out_MGT_i;  -- RAW event to MGT
  RAW_out_to_MGT_is_char <= RAW_out_char_MGT_i;  -- RAW data is char
  
  busy_raw  <= busy_raw_i ;
  
  read_on_err_out <= req_err_rd_raw_i;  -- flag requesting RAW data readout on error
 
  -- FIFO flags assignments
  RAW_data_FIFO_flags <= RAW_data_FIFO_flags_i;
 
  RAW_data_FIFO_flags_i(0) <= FIFO_RAW_Data_empty_tmp;
  RAW_data_FIFO_flags_i(1) <= FIFO_RAW_Data_prog_full_tmp;
  RAW_data_FIFO_flags_i(2) <= FIFO_RAW_Data_full_i;  -- use calculated full flag
 
  RAW_data_FIFO_flags_i(3) <= BCN_FIFO_empty_i;
  RAW_data_FIFO_flags_i(4) <= BCN_FIFO_prog_full_i;
  RAW_data_FIFO_flags_i(5) <= BCN_FIFO_full_i;
 
  RAW_data_FIFO_flags_i(6) <= Link_output_FIFO_empty_i;
  RAW_data_FIFO_flags_i(7) <= Link_output_FIFO_prog_full_i;
  RAW_data_FIFO_flags_i(8) <= Link_output_FIFO_full_i;
 
  RAW_data_FIFO_flags_i(9)            <= RAW_safe_mode_i;  -- Safe Mode operation flag for TOB readout
  RAW_data_FIFO_flags_i(10)           <= RAW_ready_in_i;  -- Ready signal from control FPGA to receive RAW calorimeter data
  RAW_data_FIFO_flags_i(11)           <= busy_raw_i;      -- BUSY signal from proc FPGA to stop L1A signal
  RAW_data_FIFO_flags_i(31 downto 12) <= (others => '0');
 
  RAW_FIFO_data_count <= data_count_i(20);  -- use a value in the middle of pFPGA for ease of use
 
  link_error_flags <= FIFO_error_flags_54b_i;  -- error flags from the ERROR FLag FIFO
  
  raw_fsm_monitor <= X"00" & raw_data_mgt_fsm_i & raw_data_mux_fsm_i & raw_data_dpram_fsm_i ;
 
U0_clk : process (clk_in_280M_i)
    begin
      if rising_edge (clk_in_280M_i) then
        FIFO_RAW_Data_prog_full_tmp <= OR FIFO_RAW_Data_prog_full_i;
        FIFO_RAW_Data_empty_tmp     <= OR FIFO_RAW_Data_empty_i;
      end if;
    end process;
 
-- this FDCE regitsters the cFPGA Ready input signal to receive RAW Data.
  U0_FDCE_inst : FDCE
    generic map (
      INIT => '0')        -- Initial value of register ('0' or '1')
    port map (
      Q   => RAW_ready_in_i,      -- Data output
      C   => clk_in_280M_i,      -- Clock input
      CE  => '1',                -- Clock enable input
      CLR => '0',
      D   => RAW_ready_in  -- Ready signal from control FPGA to receive RAW calorimeter data
      );
 
-- the FSM regitsters occupancy of RAW data FIFO to send RAW BUSY signal to cFPGA
U1_busy_flag_fsm : entity TOB_rdout_lib.busy_flag_fsm
    generic map ( 
        width => 9
        )
    port map (
       clk => clk_in_280M_i,
       rst => RAW_FIFO_sw_rst_i,
       busy_flag_assert => raw_busy_thresh_assert,
       busy_flag_negate => raw_busy_thresh_negate, 
       fifo_data_count  => data_count_i(22), -- use fibre 22 to ease timing, may be different for different FPGAs 
       busy_flag => busy_raw_i
    );
 
-- The GEN_CHANNEL loop, generates 49 copies of the RAW data readout blocks within it,these are:
--     PISO unit - to convert data from 224b to 7 x 32b words
--     Dual Port RAM - scrolling memory to store data on every bunch crossing
--         This is circular Dual Port RAM. It stores 7x32b words per Bunch number.
--         the DPRAM is 36b wide, and bits 35 to 32 are used to store the 4b error flags for the corresponding MGT Channel.
--         The Read and Write address have the correct offset in order to read the actual RAW data
--         associated with the BCN at the time of arrival of L1A
--    Derandomisation FIFO - to store the correct data word upon receiving an L1A
--         This is Derandomisation FIFO. It stores 7x32b words per L1A, which are read out of Circular memory.
--         The FIFO is 36b wide, bits 35:32 are used to store the 4b error flags for the corresponding MGT Channel.
 
GEN_CHANNEL : for i in 0 to chan_no-1 generate  -- generate for 49 links (chan_no= 49)
 
-- This module generates a synch signal synchronised to 40MHz and 280MHz clocks
-- one synch pulse is generated - this is 1 in 7 sync'ed to 40M clock
  U1_gen_sync_280 : entity TOB_rdout_lib.gen_sync_280M
    port map(
      RST           => RST_i,           -- RST from 40MHz MMCM lock signal
      clk_40M       => clk_40M_rdout,   -- Clock 40MHz
      clk_280M      => clk_in_280M_i,
      sync_280m_out => sync_280m_i(i)      -- this is 1 in 7 sync'ed to 40M clk
      );
 
-- Pipelines the input RAW data by one 40 MHz clock to move away from the real time circuit
    proc1 : process (clk_40M_rdout)
    begin
      if rising_edge (clk_40M_rdout) then
        RAW_data_in_1dly(i) <= RAW_data_in(i);
--        delayed_crc_error_i(i)   <= RAW_data_in_1dly(i)(226)  ;
      end if;
    end process;
 
--    PISO unit - to convert data from 224b to 7 x 32b words
    U2_PISO_RAW : entity TOB_rdout_lib.PISO_RAW_data  -- convert 224b to 7 x 32b words for Circular DPR
      port map (
        RST              => RAW_FIFO_sw_rst_i,  -- rst by s/w or RST from 40MHz MMCM lock signal
        RAW_link_data_in => RAW_data_in_1dly(i),  -- 227b  words for Circular DPR
        data_sync_in     => sync_280m_i(i),  -- this is 1 in 7 sync'ed to 40M clk
        clk_in_280M      => clk_in_280M_i,
        data_sync_out    => PISO_sync_out_i(i),
        data_out_valid   => PISO_data_out_valid_i(i),
        data_out         => PISO_data_out_i(i)  -- 7x36b RAW data to DPRAM + 4b error (use J)
        );
 
-- RAW Data Circular DPRAM input 36b = ORed 4-bit links error flags + 32-bit Raw Data
    U3_DPRAM_RAW_Data : DPR_36b_1024     -- it is in the IP package
      port map (
        clka  => clk_in_280M_i,         -- runs at 200M but writes 1 in 5 clks
        ena   => '1',                   -- clk/rst en for DPRAM port A
        wea   => stdv(PISO_data_out_valid_i(i)),  -- this is wr en using PISO_data_out_valid_i
        addra => DPR_wr_addr_i_1dly,    -- TD_LOGIC_VECTOR(8 DOWNTO 0)
        dina  => PISO_data_out_i(i),  -- 7x32b RAW data from DPRAM into FIFO + 4b error
        clkb  => clk_in_280M_i,
        enb   => DRP_rd_en_i_1dly,      -- clk/rst/addr en for DPRAM port B
        addrb => DPR_rd_addr_i_1dly,    --
        doutb => DPR_RAW_out_i(i)  -- 7x36b RAW data from DPRAM to FIFO array 49 of 36b = err + data to remove timing error
        );
 
-- RAW Data FIFO input 36b = ORed 4-bit links error flags + 32-bit Raw Data
    U4_FIFO_RAW_Data : FIFO_36b_512  -- the flags from these 49 FIFOs are not used
      port map (  -- if backpressure goes on we stop capturing data
        srst                    => RAW_FIFO_sw_rst_i,  -- sys RST OR RAW_FIFO_sw_rst
        clk                     => clk_in_280M_i,
        din                     => DPR_RAW_out_i_1dly(i),    --  DPRAM register enabled
        wr_en                   => FIFO_wr_en_i_2dly(i),  --  i/p delayed version of FIFO_wr_en
        rd_en                   => FIFO_rd_en_i(i),
        dout                    => FIFO_RAW_Data_dout_i(i),  -- array 49 of 36b = err + data
        valid                   => FIFO_RAW_Data_valid_i(i),  -- 49 sync signals for 49 links
        prog_full_thresh_assert => RAW_data_FIFO_pFULL_THRESH_assert_i,  -- 9b
        prog_full_thresh_negate => RAW_data_FIFO_pFULL_THRESH_negate_i,
        data_count              => data_count_i(i),
        prog_full               => FIFO_RAW_Data_prog_full_i(i),
        full                    => open,
        empty                   => FIFO_RAW_Data_empty_i(i)
        );
 
-- AS there are too much path delay between DPRAM and FIFO untis on some input channels,
-- a register has been added to allow for the path delay, and remove timing error.
    U5_1_clk : process (clk_in_280M_i)
    begin
      if rising_edge (clk_in_280M_i) then
        -- register signals to meet timing
        FIFO_RAW_Data_dout_i_1dly(i)  <= FIFO_RAW_Data_dout_i(i);  -- register the array 49 of 36b = err + data to remove timing error
        FIFO_RAW_Data_valid_i_1dly(i) <= FIFO_RAW_Data_valid_i(i);  -- register the  49 sync signals for 49 links
 
        DPR_RAW_out_i_1dly(i)   <= DPR_RAW_out_i(i);  -- register the array 49 of 36b = err + data to remove timing error
        link_error_flags_tmp(i) <= DPR_RAW_out_i_1dly(i)(35 downto 32);  -- array of 4 ERROR bits for each MGT input link
        
        FIFO_wr_en_i_2dly(i)  <= FIFO_wr_en_i_1dly and (not(FIFO_RAW_Data_prog_full_i(i)));
 
      end if;
    end process;
 
  end generate GEN_CHANNEL;
 
 
-- OR all the input error flags together to create the 4-bit error signal to be added to the event
-- Also check the 4-bit error flag to create 1-b flag to request data on error
  U5_link_err : entity TOB_rdout_lib.link_errors_ORed
    generic map
    (N => 49)
    port map
    (clk_in            => clk_in_280M_i,
     rst_in            => RAW_FIFO_sw_rst_i,
     err_flag_in       => link_error_flags_tmp, -- array of 4 ERROR bits for each MGT input (zero + input_crc + input_disparity + not_in_table)
     en_error_valid_in => en_error_valid_3dly,  -- Enable capture of error flags from last RAW input data
     err_flag_out      => link_err_4b_in_i,     -- 4-bit link error ouput to RAW readout (zero + input_crc + input_disparity + not_in_table)
     channel_error_map => channel_error_49b_i,  -- 49-bit channel error map to input into RAW readout
     req_err_rd_raw    => req_err_rd_raw_i      -- flag requesting RAW data readout on error
     );
 
 
-- this FDCE regitsters the L1A_in signal to act as write signal for Link Errors FIFO
  U5_FDCE_inst : FDCE
    generic map (
      INIT => '0')           -- Initial value of register ('0' or '1')
    port map (
      Q   => L1A_in_1dly,               -- Data output
      C   => clk_40M_rdout,             -- Clock input
      CE  => '1',                       -- Clock enable input
      CLR => '0',  -- async rst by s/w or RST from 40MHz MMCM lock signal
      D   => L1A_in_i                   -- Data input
      );
 
  -- input to Link Error FIFO = requesting RAW data readout + ORed 4-bit link error + 49-bit channel error map
  -- (errors = zero + input_crc + input_disparity + not_in_table)
  link_error_flags_54b_i <= req_err_rd_raw_i & link_err_4b_in_i & channel_error_49b_i;
 
-- This modules is the Link Errors FIFO..
-- It stores the following information for use in the construction of RAW Events:
-- Link Error FIFO input 54b = 1-bit RAW data readout on error + ORed 4-bit links error flags + 49-bit channel error map.
  U5_FIFO_link_err : FIFO_54b_512
    port map (
      rst    => RAW_FIFO_sw_rst_i,      -- sys RST OR RAW_FIFO_sw_rst
      wr_clk => clk_in_280M_i,
      rd_clk => clk_in_280M_i,
      din    => link_error_flags_54b_i,
      wr_en  => en_error_valid_4dly,
      rd_en  => BCN_FIFO_rd_en_i,
      dout   => FIFO_error_flags_54b_i,
      valid  => FIFO_error_flags_valid_i,
      full   => open,
      empty  => link_err_FIFO_empty_i
      );
 
-- This FSM is responsible for transfering the correct RAW data values from the Circular DPRAMs to de-randomisation FIFOs.
-- The control signals ensure all 49 DPRAMs are read and written to 49 FIFOs in parallel.
-- The write address offset for SPRAM ensures the data associated with required BCN is read out.
-- When the prog_FULL flag of de-randomisation FIFO is set to 1, no more data is written to this FIFO
  U5_RAW_fsm : entity TOB_rdout_lib.fsm_RAW_data_wr_to_DPR
    port map (
      CLK_280M       => clk_in_280M_i,
      RST            => RAW_FIFO_sw_rst_i,  -- sys RST OR RAW_FIFO_sw_rst
      L1A_in         => L1A_in_i,
      pre_ld_wr_addr => pre_ld_wr_addr,
      DPR_rd_addr    => DPR_rd_addr_i,
      DPR_wr_addr    => DPR_wr_addr_i,
      DRP_rd_en      => DRP_rd_en_i,
      FIFO_wr_en     => FIFO_wr_en_i,   -- o/p
      en_error_valid => en_error_valid_i,  -- o/p Enable capture of error flags from last RAW word
      raw_data_dpram_fsm => raw_data_dpram_fsm_i
      );
 
-- Module gen_full_flag monitors the occupancy level of one de-randomisation FIFO for channel 20.
-- Channel 20 has been chosen in order to be in the middle of the FPGA, but any other channel can be selected.
-- The programmable Assert and Negate registers control the occupancy levels at which the FULL Flag is asserted and negated.
  U5b_gen_full_flag : entity TOB_rdout_lib.RAW_fifo_full_flag_gen
    port map (
      rst_in          => RAW_FIFO_sw_rst_i,
      clk_in          => clk_in_280M_i,
      fifo_data_count => data_count_i(20),  -- use 20 to be in the middle of pFPGA
      assert_count_in => RAW_FIFO_FULL_THRESH_ASSERT,
      negate_count_in => RAW_FIFO_FULL_THRESH_NEGATE,
      full_flag_out   => FIFO_RAW_Data_full_i
      );
 
-- pipeline registers to meet timing
  U5c_1_clk : process (clk_in_280M_i)
  begin
    if rising_edge (clk_in_280M_i) then
      DPR_rd_addr_i_1dly <= DPR_rd_addr_i;
      DPR_wr_addr_i_1dly <= DPR_wr_addr_i;
      DRP_rd_en_i_1dly   <= DRP_rd_en_i;
      FIFO_wr_en_i_1dly  <= FIFO_wr_en_i;  -- register wr signals for 49 links
 
      en_error_valid_1dly <= en_error_valid_i;     -- delay error flags valid by 1 clk
      en_error_valid_2dly <= en_error_valid_1dly;  -- delay error flags valid by 1 clk
      en_error_valid_3dly <= en_error_valid_2dly;  -- delay error flags valid by 1 clk
      en_error_valid_4dly <= en_error_valid_3dly;  -- delay error flags valid by 1 clk
    end if;
  end process;
 
  -- write L1A number and BC number into FIFO
  -- 1b FIFO_RAW_Data_prog_full_i + 0 + 1b Privilege Read + 12b BCN_ID_in + 8b ECID + 24b L1A_ID_in
  BCN_FIFO_Data_in_i <= FIFO_RAW_Data_prog_full_tmp & '0' & TTC_read_all_in & BCN_ID_in & L1A_ID_in;
 
-- This is TTC FIFO for RAW Data Readout, which stores the following values:.
-- bit 46 = Safe Mode bit set by TTC FIFO full flag.
-- bit 45 = not used
-- bit 44 = privilege read flag
-- bits 43:32 = Bunch Crossing Number - generated in pFPGA
-- bits 31:24 = Extended L1A - received from CFPGA
-- bits 23:0  = L1A_ID - received from cFPGA
  U6_FIFO_BCN_L1A : FIFO_47b_512        -- the flags from this FIFO is used
    port map (
      rst                     => RAW_FIFO_sw_rst_i,  -- sys RST OR RAW_FIFO_sw_rst
      wr_clk                  => clk_40M_rdout,
      rd_clk                  => clk_in_280M_i,
      din                     => BCN_FIFO_Data_in_i,
      wr_en                   => L1A_in_i,
      rd_en                   => BCN_FIFO_rd_en_i,
      dout                    => BCN_FIFO_Data_out_i,
      valid                   => BCN_FIFO_valid_i,
      rd_data_count           => BCN_FIFO_RAW_rd_data_count,
      prog_full_thresh_assert => BCN_FIFO_pFULL_THRESH_assert_i,
      prog_full_thresh_negate => BCN_FIFO_pFULL_THRESH_negate_i,
      prog_full               => BCN_FIFO_prog_full_i,
      full                    => BCN_FIFO_full_i,
      empty                   => BCN_FIFO_empty_i
      );
 
-- This is FSM to read RAW data from de-randomisation FIFOs and write into link output FIFO.
-- This FSM also handles Header and Trailer construction.
--
-- Under normal operation mode, only MGT channels with error flag set, are added to the RAW data event frame.
-- If there are no errors, then an event is generated with 2 header and 1 trailer words, and the payload is two 32-b words
-- containing the error flags of all 49 MGT channels.
--
-- If Privilege Read flag or Read_RAW_all flag is set, then the RAW data for all MGT channels are added to the RAW data event frame.
-- Read_RAW_all flag is bit 1 of Test_Contol_Reg register.
--
-- Under Safe Mode Operation, the occupancy of TTC FIFO are monitored.
-- If the occupancy reaches a programmable threshold, empty events are generated which consits of 2 header and 1 trailer words.
--
-- The output of this FSM is:
--     32-bit data word
--     1-bit data is CHAR
--     1-bit valid which is the write enable to Link Ouput FIFO
  U7_rd_RAW_mux_fsm : entity TOB_rdout_lib.fsm_RAW_to_muxPISO
    port map (
      RST                      => RAW_FIFO_sw_rst_i,  -- sys RST OR RAW_FIFO_sw_rst
      hw_addr                  => hw_addr,
      rdout_RAW_36b_in         => FIFO_RAW_Data_dout_i_1dly,  -- raw data output of fifo -- array 49 of 36b = err + data
      valid_RAW_in             => FIFO_RAW_Data_valid_i_1dly,  -- RAW data is valid -- 49 sync signals for 49 links
      bcn_fifo_47b_in          => BCN_FIFO_Data_out_i,  -- BCN & L1A output of fifo
      valid_BCN_in             => BCN_FIFO_valid_i,  -- BCN & L1A data is valid
      FIFO_error_flags_54b     => FIFO_error_flags_54b_i,  -- 1-b request RAW data readout + ORed 4-bit link error + 49-bit channel error map
      clk_280M_in              => clk_in_280M_i,
      RAW_FIFO_prog_full_in    => FIFO_RAW_Data_prog_full_tmp,  -- i/p derandomisation FIFO prog full flag channel 19
      LO_FIFO_prog_full_in     => Link_output_FIFO_prog_full_i,  -- if link o/p FIFO pFULL discard i/p data
      LO_FIFO_data_count_in    => LO_FIFO_RAW_wr_data_count_i,  -- link o/p FIFO wr data count
      frame_cntr_en            => frame_cntr_en_i,  -- enable frame counter count up
      raw_rd_all_in            => raw_rd_all_in,  -- readout all raw data links
      RAW_rdout_fifo_rd_en_out => FIFO_rd_en_i,   -- rd enable to RAW FIFOs
      BCN_fifo_rd_en_out       => BCN_FIFO_rd_en_i,  -- rd enable to RAW data BCN FIFOs
      mgt_enable_in            => mgt_enable_in,     -- MGT enable signals - use to enable/disable readout on error
      BCN_FIFO_empty           => BCN_FIFO_empty_i,  -- input BCN L1A_ID FIFO empty flag
      BCN_FIFO_prog_full_in    => BCN_FIFO_prog_full_i,  -- i/p BCN_L1A FIFO prog full flag
      link_err_FIFO_empty      => link_err_FIFO_empty_i,  -- input link error FIFO empty flag
      RAW_out_valid            => RAW_out_valid_i,  -- sorted TOBs data valid to U7_Link_output_FIFO
      RAW_out_is_char          => RAW_out_is_char_i,  -- sorted TOBs is CHAR to U7_Link_output_FIFO
      RAW_out                  => RAW_out_i,  -- sorted TOBs valid to U7_Link_output_FIFO
      RAW_safe_mode_out        => RAW_safe_mode_i,  -- Safe Mode operation flag for EAW readout
      raw_data_mux_fsm         => raw_data_mux_fsm_i
      );
 
 
  FIFO_RAW_in_i <= RAW_out_is_char_i & RAW_out_i;  -- 1b char and 32b data
 
-- This is RAW Link Output FIFO, which stores complete RAW events (frames) ready to be transmitted to cFPGA via an MGT link at 11.2Gbps.
-- The output of FIFO is 32-bit data word, and 1-bit data is CHAR, which goes directly to MGT under FSM control.
--
-- The Frames are only transmitted when cFPGA indicates it is ready to receive data by setting ctrl_RAW_ready signal to 1.
-- If ctrl_RAW_ready signal is set to 0 by cFPGA, this indicates cFPGA is not ready to receive data,
-- in this case events accumulate in Link Output FIFO until occupancy reaches a pre-define level of prog_FULL,
-- at this time, Link Output FIFO stops receiving data.
--
-- Writing to LO FIFO is controlled by fsm_RAW_to_muxPISO FSM
-- Reading from LO FIFO is controlled by FIFO_to_MGT_RAW_FSM FSM
  U8_RAW_Link_output_FIFO : FIFO_33b_8192
    port map (
      wr_rst                  => RAW_FIFO_sw_rst_i,  -- sys RST OR RAW_FIFO_sw_rst
      wr_clk                  => clk_in_280M_i,
      wr_en                   => RAW_out_valid_i,
      din                     => FIFO_RAW_in_i,
      rd_rst                  => RAW_FIFO_sw_rst_i,  -- sys RST OR RAW_FIFO_sw_rst
      rd_clk                  => RAW_TXOUTCLK,
      rd_en                   => Link_output_FIFO_rd_en_i,
      dout                    => Link_output_FIFO_RAW_out_i,
      full                    => Link_output_FIFO_full_i,
      empty                   => Link_output_FIFO_empty_i,
      prog_full               => Link_output_FIFO_prog_full_i,
      valid                   => Link_output_FIFO_RAW_valid_i,
      prog_full_thresh_assert => Link_output_FIFO_RAW_pfull_thresh_assert_i,  -- 13b
      prog_full_thresh_negate => Link_output_FIFO_RAW_pfull_thresh_negate_i,  -- 13b
      wr_data_count           => LO_FIFO_RAW_wr_data_count_i,
      rd_data_count           => LO_FIFO_RAW_rd_data_count_i  -- 13b occupancy of Link_output_FIFO_RAW link MGT FIFO
      );
 
  Link_output_FIFO_RAW_rd_data_count <= LO_FIFO_RAW_rd_data_count_i;
 
-- This FSM reads RAW frames from Link Output FIFO and writes into MGT to transmit to cFPGA.
-- This FSM handles one full frame at a time without pausing.
-- It monitors the RAW_frame_counter to find out if there are Frames waiting to be transmitted to cFPGA.
-- The Frames are only transmitted when cFPGA indicates it is ready to receive data by setting ctrl_RAW_ready signal to 1.
-- If ctrl_RAW_ready signal is set to 0 by cFPGA, this indicates cFPGA is not ready to receive data,
-- in this case events accumulate in Link Output FIFO until occupancy reaches a pre-define prog_FULL level,
-- at this time, Link Output FIFO stops receiving data.
  U9_RAW_Link_output_FIFO_FSM : entity TOB_rdout_lib.FIFO_to_MGT_RAW_FSM
    port map (
      TOB_FIFO_sw_rst      => RAW_FIFO_sw_rst_i,  -- sys RST OR RAW_FIFO_sw_rst
      clk_in_280M          => RAW_TXOUTCLK,
      RAW_ready_in         => RAW_ready_in_i,
      frame_counter        => op_fifo_frame_count_i,
      FIFO_MGT_TOBs        => Link_output_FIFO_RAW_out_i,
      FIFO_MGT_TOB_valid   => Link_output_FIFO_RAW_valid_i,
      LO_FIFO_empty        => Link_output_FIFO_empty_i,     -- on rd clck 
      FIFO_MGT_rd_en       => Link_output_FIFO_rd_en_i,  -- output
      frame_counter_dec_en => frame_cntr_dec_en_i,
      RAW_data_out         => RAW_data_out_i,     -- RAW event to MGT
      RAW_data_is_char     => RAW_out_to_MGT_is_char_i,  -- RAW data is char
      RAW_data_out_valid   => RAW_data_out_valid_i,
      raw_data_mgt_fsm     => raw_data_mgt_fsm_i
      );
 
-- If the counter is ZERO, no data is available to be send to cFPGA.
 
U10_clk_closs_pulse : entity TOB_rdout_lib.clk_closs_pulse_fsm
    Port map ( 
       clk_src    =>  clk_in_280M_i ,
       rst_src    =>  RAW_FIFO_sw_rst_i , -- RST OR TOB_FIFO_sw_rst
       pulse_src  =>  frame_cntr_en_i,
       clk_dest   =>  RAW_TXOUTCLK ,
       pulse_dest =>  frame_cntr_en_ii 
       );
 
-- The RAW_frame_counter is a 12-bit generic up/down counter to count the number of complete Frames in Link Output FIFO to be transmitted to cFPGA.
-- When one complete Frame (event) is written to LO FIFO, this counter is incremented.
-- When one complete Frame (event) is read out LO FIFO, this counter is decremented.
-- If the counter is ZERO, no data is available to be send to cFPGA.
 
  U10_RAW_frame_counter : entity TOB_rdout_lib.cntr_up_dn_generic
    generic map (
      width => 12  -- count up to 4096 events in Link Output FIFO
      )
    port map (
      CE   => '1',
      CLK  => RAW_TXOUTCLK,
      RST  => RAW_FIFO_sw_rst_i,        -- sys RST OR RAW_FIFO_sw_rst
      UP   => frame_cntr_en_ii,         -- this is a fabric 280 MHz signal
      DOWN => frame_cntr_dec_en_i,      -- this is a TXOUTCLK 280 MHz signal
      Q    => op_fifo_frame_count_i
      );
 
-- delay data to SPY RAM
  U11_clk_proc : process (RAW_TXOUTCLK)
  begin
    if RAW_TXOUTCLK'event and RAW_TXOUTCLK = '1' then
      RAW_data_out_1dly     <= RAW_data_out_i;     -- data SPY RAM
      RAW_data_out_MGT_i    <= RAW_data_out_1dly;  -- data to MGT
      RAW_out_char_MGT_1dly <= RAW_out_to_MGT_is_char_i;
      RAW_out_char_MGT_i    <= RAW_out_char_MGT_1dly;
      RAW_out_valid_1dly    <= RAW_data_out_valid_i;
    end if;
  end process;
 
--    SPY_FIFO_RAW_in_i       <= "000" & Link_output_FIFO_RAW_out_i ;
    SPY_mem_wr_addr_en_i <= (RAW_out_valid_1dly and enable_raw_spy_mem_wr);
 
-- The RAW_SPY_mem is a Dual Port Memory with IPBus interface.
-- It is possible to read/write to/from DPRAM using the IPBus interface.
-- The SPY Memory captures the data that is read out of Link Output FIFO to MGT.
-- The SPY Memory is designed to fill up and then stops accepting new data,
-- therefore the old data is not written over.
 
  U12_RAW_SPY_mem : entity ipbus_lib.ipbus_dpram
    generic map(
      ADDR_WIDTH => 11                  -- DPRAM 512 locations
      )
    port map(
      clk     => ipb_clk,
      rst     => RST_spy_mem_wr_addr,   -- was '0',
      ipb_in  => ipbus_in_raw_dpram,    -- i/p signal going to RAW SPY DPRAM
      ipb_out => ipbus_out_raw_dpram,   -- o/p signal coming from RAW SPY DPRAM
      rclk    => RAW_TXOUTCLK,
      we      => SPY_mem_wr_addr_en_i,  -- wr addr en
      d       => RAW_data_out_1dly,     -- wr data
      q       => q_int,
      addr    => SPY_mem_wr_addr_i      -- wr addr
      );
 
-- The spy_mem_wr_addr is a generic counter that provides the write address to RAW SPY Memory.
-- The spy memory address is 11-bits wide, so the depth of memory is 2048.
-- This implies the RAW Spy Memory can hold just over 5 Full RAW Frames.
-- The write address of the RAW_SPY_mem is reset to ZERO by asserting RST_spy_mem_wr_addr or system RST signals.
-- The signal RST_spy_mem_wr_addr is bit 5 of register rdout_pulse_reg.
-- The rdout_pulse_reg register is pulsed, and after 1 clock cycle all bits are reset to Zeros.
 
  U13_spy_mem_wr_addr : entity TOB_rdout_lib.cntr_generic
    generic map (
      width => 11
      )
    port map (
      CE  => SPY_mem_wr_addr_en_i,  -- if a valid data, then increment the address
      CLK => RAW_TXOUTCLK,
      RST => RST_spy_mem_wr_addr,
      Q   => SPY_mem_wr_addr_i
      );
 
-- Process U14_stop_wr disables the write enable signal to Spy Memory when it is full.
 
  U14_stop_wr : process (RAW_TXOUTCLK)
  begin
    if rising_edge (RAW_TXOUTCLK) then
      if (RST_spy_mem_wr_addr = '1') then
        enable_raw_spy_mem_wr <= '1';   -- if not full, en data wr
      else
        if SPY_mem_wr_addr_i = "11111111111" then  -- if terminal count -1 to prevent wrap round to ZERO
          enable_raw_spy_mem_wr <= '0';  -- disable memory wr to prevent data corruption
        end if;
      end if;
    end if;
  end process U14_stop_wr;
 
 
end RTL;