fsm_RAW_to_muxPISO Entity Reference

FSM to write RAW calolimeter data to Link Output FIFO for process FPGA. More...

Inheritance diagram for fsm_RAW_to_muxPISO:

Entities
Behavioral	architecture
	FSM to write RAW calolimeter data to Link Output FIFO for process FPGA. More...

Libraries
IEEE
TOB_rdout_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
data_type_pkg	Package <data_type_pkg>

Ports
RST	in	std_logic
hw_addr	in	STD_LOGIC_VECTOR ( 1 downto 0 )
		FPGA Hardware Address.
rdout_RAW_36b_in	in	DPR_RAW_out_36_type
		raw data 36b = 4b+32b ERR+RAW
valid_RAW_in	in	t_49_arr_1b
		RAW data valid signal.
bcn_fifo_47b_in	in	STD_LOGIC_VECTOR ( 46 downto 0 )
		BCN fifo data 47b = 1b FIFO_RAW_Data_prog_full_i + 0 + 1b Privilege Read + 12b BCN_ID_in + 32b L1A_ID_in.
valid_BCN_in	in	std_logic
		RAW data valid signal.
FIFO_error_flags_54b	in	STD_LOGIC_VECTOR ( 53 downto 0 )
		Link Error FIFO = ZERO + 1-b request RAW data on error + ORed 3-bit link error + 49-bit channel error map.
clk_280M_in	in	STD_LOGIC
		fabric 280MHz clock
RAW_FIFO_prog_full_in	in	std_logic
		RAW Input FIFO partial FULL flag.
LO_FIFO_prog_full_in	in	std_logic
		Link Output FIFO partial FULL flag to receive RAW calorimeter data.
LO_FIFO_data_count_in	in	STD_LOGIC_VECTOR ( 12 downto 0 )
		Link Output FIFO data count.
frame_cntr_en	out	STD_LOGIC
		Comp;leted frame counter enable.
raw_rd_all_in	in	STD_LOGIC
		readout all raw data links
RAW_rdout_fifo_rd_en_out	out	t_49_arr_1b
		read enable signal to all RAW data FIFOs
BCN_fifo_rd_en_out	out	STD_LOGIC
		read enable signal to BCN & L1A FIFOs
mgt_enable_in	in	STD_LOGIC_VECTOR ( 48 downto 0 )
		MGT enable signals - use to enable readout on error.
BCN_FIFO_empty	in	STD_LOGIC
		FIFO empty flag from BCN L1A FIFO.
BCN_FIFO_prog_full_in	in	STD_LOGIC
		BCN & L1A FIFO prog full flag.
link_err_FIFO_empty	in	STD_LOGIC
		FIFO empty flag from link error FIFO.
RAW_out_valid	out	STD_LOGIC
		RAW data valid signal to Link_outpout_FIFO.
RAW_out_is_char	out	STD_LOGIC
		RAW data is CHAR signal to Link_outpout_FIFO.
RAW_out	out	STD_LOGIC_VECTOR ( 31 downto 0 )
		RAW data 32b to Link_outpout_FIFO.
RAW_safe_mode_out	out	STD_LOGIC
		Safe Mode operation flag for RAW readout.
raw_data_mux_fsm	out	STD_LOGIC_VECTOR ( 7 downto 0 )
		Monitor state machine status register.

Detailed Description

FSM to write RAW calolimeter data to Link Output FIFO for process FPGA.

This module creates a complete RAW calolimeter event together with Header and Trailer and writes the entire event into Link Output FIFO. The Link Output FIFO is then controlled by FIFO_to_MGT_FSM state machine to transfer data to MGT. This FSM also handles Header and Trailer construction.

In order to create one full RAW event (frame) all 49 fibre channels must be read in turn from channel 0 to channel 48, This proces takes 599 ticks of 280MHz clock, approximately 2139 ns.

Under normal operation mode, only MGT channels with error flag set, are added to the RAW data event frame. If there are no errors, then an event is generated with 2 header and 1 trailer words, and the payload is two 32-b words containing the error flags of all 49 MGT channels. In this case generating a RAW Event takes only 16 ticks of 280MHz clock, approximately 57.143 ns.

If Privilege Read flag or Read_RAW_all flag is set, then the RAW data for all MGT channels are added to the RAW data event frame. Read_RAW_all flag is bit 1 of Test_Contol_Reg register. The Privilege Read flag is bit 9 of TTC B-channel command. Privilege Read or Read_RAW_all, generate a full event which also takes 598 ticks of 280MHz clock, approximately 2135 ns.

Under Safe Mode Operation, the occupancy of TTC FIFO are monitored. If the occupancy reaches a programmable threshold, empty events are generated which consits of 2 header and 1 trailer words. The RAW Event under safe mode operation is 11 ticks of 280MHz clock, approximately 39.29 ns

The output of this FSM is: 32-bit data word 1-bit data is CHAR 1-bit valid which is the write enable to Link Output FIFO

Header Word 1:

• RAW_out_i(31:20) = ZERO
• RAW_out_i(19:8) = Local (internal) BCN
• RAW_out_i(7:0) = ch_sop2 = X"7C"

Header Word 2:

• RAW_out_i(31:24) = Extended L1_ID
• RAW_out_i(23:0) = Level 1 ID

Fibre Trailer Word:

• RAW_out_i(31:28) = link error (4b = mgt_disable + input_crc + input_disparity + not_in_table)
• RAW_out_i(27:10) = ZERO
  
• RAW_out_i(9:8) = FPGA Number
• RAW_out_i(7:0) = Optical Link Number

Trailer Word 1:

• RAW_out_i(31:0) = channel_error_map(31 downto 0); – 32b channel error map

Trailer Word 2:

• RAW_out_i(31:27) = link error (4b = read_on_error + input_crc_all + input_disparity_all + not_in_table_all + raw_rd_all)
  
• RAW_out_i(26:17) = ZERO
  
• RAW_out_i(16:0) = channel_error_map(48 downto 32); – 17b channel error map

Trailer Word 3:

• RAW_out_i(31) = safe_mode_i
• RAW_out_i(30:20) = ZERO
• RAW_out_i(19:8) = RAW Payload Counter
• RAW_out_i(7:0) = ch_eop = X"DC"

CHAR constants are defined in data_type_pkg.vhd for reference only constant ch_idle : std_logic_vector(7 downto 0) := X"BC" ; – idle char is K28.5 constant ch_sop1 : std_logic_vector(7 downto 0) := X"3C" ; – TOB/XTOB star of packet char is K28.1 constant ch_sop2 : std_logic_vector(7 downto 0) := X"7C" ; – CALO DATA star of packet char is K28.3 constant ch_eop : std_logic_vector(7 downto 0) := X"DC" ; – end of packet char is K28.6

Author

Saeed Taghavi

Definition at line 79 of file fsm_RAW_to_muxPISO.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/fsm_RAW_to_muxPISO.vhd