Behavioral Architecture Reference

FSM to write RAW calolimeter data to Link Output FIFO for process FPGA. More...

Processes
U3A_proc1	( CLK_280M_i )
U4_rd_fsm	( CLK_280M_i )

Constants
FPGA_mapping	FPGA_mapping_array := ( " 10 " , " 01 " , " 11 " , " 00 " )
LO_almost_full_value	unsigned := X " 1FF0 "

Types
FPGA_mapping_array	( 3 downto 0 ) std_logic_vector ( 1 downto 0 )
STATE_TYPE	( idle , wait_1 , wait_2 , wait_3 , wait_4 , wait_5 , wait_6 , wait_7 , wait_8 , start , pause , hdr_sel , err_sop , err_eop , BCN_wait , norm_sop_1 , norm_sop_2 , norm_tlr , norm_eop , rd_bcn_fifo , empty_raw_fifo , rdout_raw_1 , rdout_raw_2 , rdout_raw_3 , rdout_raw_4 , rdout_raw_5 , rdout_raw_6 , rdout_raw_7 , sub_trl_1 , sub_trl_2 )

Signals
RAW_out_valid_i	std_logic
RAW_rdout_fifo_rd_en_i	t_49_arr_1b
BCN_fifo_rd_en_out_i	std_logic
rec_err_flg_4b_i	STD_LOGIC_VECTOR ( 3 downto 0 )
rd_on_err_en_i	std_logic
BCN_in_i	STD_LOGIC_VECTOR ( 11 downto 0 )
valid_BCN_i	STD_LOGIC
L1A_ID_in_i	STD_LOGIC_VECTOR ( 23 downto 0 )
L1A_ID_EXT_in_i	STD_LOGIC_VECTOR ( 7 downto 0 )
FIFO_RAW_Data_prog_full_i	STD_LOGIC
ORed_err_flg_i	STD_LOGIC
mgt_disable_i	STD_LOGIC
RAW_out_i	STD_LOGIC_VECTOR ( 31 downto 0 )
RAW_out_is_char_i	std_logic
CLK_280M_i	std_logic
RST_i	std_logic
payld_cntr_rst	std_logic
payld_cntr_rst_i	std_logic
payld_cntr_en	std_logic
raw_payld_cntr_i	std_logic_vector ( 11 downto 0 )
frame_cntr_en_i	std_logic
write_in_LO_FIFO_i	std_logic
RAW_in_i	DPR_RAW_out_36_type
RAW_in_tmp	DPR_RAW_out_36_type
RAW_in_valid_i	t_49_arr_1b
RAW_in_valid_tmp	t_49_arr_1b
opt_link_num_i	std_logic_vector ( 7 downto 0 ) := " 00000000 "
fpga_num_i	std_logic_vector ( 1 downto 0 ) := " 00 "
raw_rd_all_in_i	std_logic
safe_mode_i	std_logic
BCN_FIFO_empty_i	std_logic
link_err_FIFO_empty_i	std_logic
BCN_FIFO_prog_full_in_i	std_logic
links_err_4b_in_i	std_logic_vector ( 3 downto 0 )
channel_error_map_i	STD_LOGIC_VECTOR ( 48 downto 0 )
channel_error_rdout_i	STD_LOGIC_VECTOR ( 48 downto 0 )
current_state	STATE_TYPE
i	integer range 0 to 50
ii	integer range 0 to 8

Attributes
keep	string
max_fanout	integer
keep	signal is " true "
max_fanout	signal is 30

Instantiations
u3_raw_payld_length	cntr_generic <Entity cntr_generic>

Detailed Description

FSM to write RAW calolimeter data to Link Output FIFO for process FPGA.

This module creates a complete RAW calolimeter event together with Header and Trailer and writes the entire event into Link Output FIFO. The Link Output FIFO is then controlled by FIFO_to_MGT_FSM state machine to transfer data to MGT. This FSM also handles Header and Trailer construction.

In order to create one full RAW event (frame) all 49 fibre channels must be read in turn from channel 0 to channel 48, This proces takes 599 ticks of 280MHz clock, approximately 2139 ns.

Under normal operation mode, only MGT channels with error flag set, are added to the RAW data event frame. If there are no errors, then an event is generated with 2 header and 1 trailer words, and the payload is two 32-b words containing the error flags of all 49 MGT channels. In this case generating a RAW Event takes only 16 ticks of 280MHz clock, approximately 57.143 ns.

If Privilege Read flag or Read_RAW_all flag is set, then the RAW data for all MGT channels are added to the RAW data event frame. Read_RAW_all flag is bit 1 of Test_Contol_Reg register. The Privilege Read flag is bit 9 of TTC B-channel command. Privilege Read or Read_RAW_all, generate a full event which also takes 598 ticks of 280MHz clock, approximately 2135 ns.

Under Safe Mode Operation, the occupancy of TTC FIFO are monitored. If the occupancy reaches a programmable threshold, empty events are generated which consits of 2 header and 1 trailer words. The RAW Event under safe mode operation is 11 ticks of 280MHz clock, approximately 39.29 ns

The output of this FSM is: 32-bit data word 1-bit data is CHAR 1-bit valid which is the write enable to Link Output FIFO

Header Word 1:

• RAW_out_i(31:20) = ZERO
• RAW_out_i(19:8) = Local (internal) BCN
• RAW_out_i(7:0) = ch_sop2 = X"7C"

Header Word 2:

• RAW_out_i(31:24) = Extended L1_ID
• RAW_out_i(23:0) = Level 1 ID

Fibre Trailer Word:

• RAW_out_i(31:28) = link error (4b = mgt_disable + input_crc + input_disparity + not_in_table)
• RAW_out_i(27:10) = ZERO
  
• RAW_out_i(9:8) = FPGA Number
• RAW_out_i(7:0) = Optical Link Number

Trailer Word 1:

• RAW_out_i(31:0) = channel_error_map(31 downto 0); – 32b channel error map

Trailer Word 2:

• RAW_out_i(31:27) = link error (4b = read_on_error + input_crc_all + input_disparity_all + not_in_table_all + raw_rd_all)
  
• RAW_out_i(26:17) = ZERO
  
• RAW_out_i(16:0) = channel_error_map(48 downto 32); – 17b channel error map

Trailer Word 3:

• RAW_out_i(31) = safe_mode_i
• RAW_out_i(30:20) = ZERO
• RAW_out_i(19:8) = RAW Payload Counter
• RAW_out_i(7:0) = ch_eop = X"DC"

CHAR constants are defined in data_type_pkg.vhd for reference only constant ch_idle : std_logic_vector(7 downto 0) := X"BC" ; – idle char is K28.5 constant ch_sop1 : std_logic_vector(7 downto 0) := X"3C" ; – TOB/XTOB star of packet char is K28.1 constant ch_sop2 : std_logic_vector(7 downto 0) := X"7C" ; – CALO DATA star of packet char is K28.3 constant ch_eop : std_logic_vector(7 downto 0) := X"DC" ; – end of packet char is K28.6

Author

Saeed Taghavi

Definition at line 134 of file fsm_RAW_to_muxPISO.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/fsm_RAW_to_muxPISO.vhd