fsm_RAW_data_wr_to_DPR.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
library TOB_rdout_lib;
use TOB_rdout_lib.TOB_rdout_ip_pkg.ALL;
use TOB_rdout_lib.data_type_pkg.all;
 
entity fsm_RAW_data_wr_to_DPR is
    Port ( 
       CLK_280M              : in STD_LOGIC;
       RST                   : in STD_LOGIC;
       L1A_in                : in STD_LOGIC;
       pre_ld_wr_addr        : in STD_LOGIC_VECTOR (9 downto 0);
       DPR_rd_addr           : out STD_LOGIC_VECTOR (9 downto 0);
       DPR_wr_addr           : out STD_LOGIC_VECTOR (9 downto 0);
       DRP_rd_en             : out STD_LOGIC ;
       FIFO_wr_en            : out STD_LOGIC ;      -- en wr into FIFO
       en_error_valid        : out STD_LOGIC;
       raw_data_dpram_fsm        : out STD_LOGIC_VECTOR (7 downto 0)
       );  
       end fsm_RAW_data_wr_to_DPR;
 
architecture Behavioral of fsm_RAW_data_wr_to_DPR is
 
    signal  CLK_280M_i              : std_logic ;
    signal  RST_i                   : std_logic ;
    signal  L1A_in_1      : std_logic ;
    signal  FIFO_wr_en_i            : std_logic := '0' ;
    signal  FIFO_wr_en_tmp          : std_logic := '0' ;
    signal  DRP_rd_en_i             : std_logic ;
    signal  en_error_valid_i        : std_logic ;
    signal  DPR_rd_addr_i           : STD_LOGIC_VECTOR (9 downto 0);
    signal  DPR_wr_addr_i           : STD_LOGIC_VECTOR (9 downto 0);
 
    TYPE STATE_TYPE IS (
       idle,
       rd_mem,
       wait_1,
       ser_1,
       ser_2,
       ser_3,
       ser_4
       );
  
    SIGNAL current_state : STATE_TYPE;    
    signal count : integer range 0 to 8;
    
--   ####### Mark  signals  ########
     attribute keep       : string ;
     attribute max_fanout : integer;
     attribute keep of       FIFO_wr_en_i  : signal is "true" ;
     attribute max_fanout of FIFO_wr_en_i  : signal is 30;
     attribute keep of       DRP_rd_en_i   : signal is "true" ;
     attribute max_fanout of DRP_rd_en_i   : signal is 30;
     attribute keep of       DPR_rd_addr_i : signal is "true" ;
     attribute max_fanout of DPR_rd_addr_i : signal is 30;
     attribute keep of       DPR_wr_addr_i : signal is "true" ;
     attribute max_fanout of DPR_wr_addr_i : signal is 10;
     attribute keep of       pre_ld_wr_addr : signal is "true" ;
     attribute max_fanout of pre_ld_wr_addr : signal is 30;
--   #######################################
    
begin
 
    CLK_280M_i      <= CLK_280M ;
    RST_i           <= RST ;
    
    DRP_rd_en       <= DRP_rd_en_i ;
    DPR_rd_addr     <= DPR_rd_addr_i ;
    FIFO_wr_en      <= FIFO_wr_en_i ;   -- was FIFO_wr_en_tmp
    DPR_wr_addr     <= DPR_wr_addr_i ;
    en_error_valid  <= en_error_valid_i; -- disable capture of error flags from last RAW word
 
    
-- The U2_rd_addr counter generates the read address for circular Dual Port RAM.
-- For every cycle of the 280 MHz clock, this counter is incremented. 
-- This counter wraps round to ZERO when it reaches full count.
-- The write address of the Dual Port RAM is generated by adding the programmable Offset Value with Read Address.
-- Therefore: write address = read_addr + offset
 
U2_rd_addr : entity work.cntr_ram_addr_10b
    Port map (                                        
       CE       => '1' ,    -- needs to count at 280MHz
       CLK      => CLK_280M_i ,
       RST      => RST_i,
       Q        => DPR_rd_addr_i 
       );         
       
    -- write address = read_addr + offset
    DPR_wr_addr_i     <= std_logic_vector ( unsigned(pre_ld_wr_addr) + unsigned(DPR_rd_addr_i) )  ;                                
 
-- Upon receiving an L1A, this process transfers 7 x 32-b words from the Circular DPRAM to the de-randomisation FIFO.  
--
U3_rd_fsm : process (CLK_280M_i)
    -- reads data from DPRAM to FIFO     
    begin
        if CLK_280M_i'event and CLK_280M_i = '1' then
            L1A_in_1        <= L1A_in ;
            if RST_i = '1' then
                FIFO_wr_en_i    <= '0' ;
                DRP_rd_en_i     <= '0' ;
                en_error_valid_i <= '0';    -- disable capture of error flags from last RAW word
                count           <= 0 ;
                current_state   <= idle ;
                raw_data_dpram_fsm <= x"00";
            else  
                CASE current_state is
                    when idle =>
                        count <= 0 ; 
                        FIFO_wr_en_i    <= '0';
                        DRP_rd_en_i     <= '0' ;
                        en_error_valid_i <= '0';    -- disable capture of error flags from last RAW word
                        raw_data_dpram_fsm <= x"01";
                        if L1A_in_1 = '1' then  -- on L1A rd data from FIFO into DPRAM
                            current_state   <= rd_mem ;   -- 1 clk extra delay for data to come out of DPRAM internal register
                        else
                            current_state   <= idle ;
                        end if;
                        
                    when rd_mem =>  -- 1 clk for data to come out of DPRAM 
                        DRP_rd_en_i     <= '1' ;
                        FIFO_wr_en_i    <= '0';
                        current_state <= wait_1 ;
                        raw_data_dpram_fsm <= x"02";
                        
                    when wait_1 =>  -- 1 clk for data to come out of DPRAM 
                        DRP_rd_en_i     <= '1' ;
                        FIFO_wr_en_i    <= '1';
                        en_error_valid_i <= '1';    -- enable capture of error flags from RAW word
                        current_state <= ser_1 ;
                        count <= count + 1 ;
                        raw_data_dpram_fsm <= x"03";
                            
                    when ser_1 =>
                        en_error_valid_i <= '0';
                        raw_data_dpram_fsm <= x"04";
                        if  count < 6 then      -- this is 6th word
                            DRP_rd_en_i     <= '1' ;
                            FIFO_wr_en_i    <= '1';
                            count <= count + 1 ;
                            current_state <= ser_1 ;
                        else
                            en_error_valid_i <= '0';    -- enable capture of error flags from last RAW word
                            if  L1A_in_1 = '1' then         -- if L1A = 1
                                DRP_rd_en_i     <= '1' ;
                                FIFO_wr_en_i    <= '1';     -- to capture the 7th data word from DPRAM
                                count <= 0 ;
                                current_state <= wait_1 ;   -- 1 clk for data to come out of DPRAM
                            else
                                 current_state <= idle ;
                                 DRP_rd_en_i   <= '0' ;
                                 FIFO_wr_en_i  <= '1' ;     -- to capture the 7th data word from DPRAM
                                 count <= 0 ;
                            end if; 
                    end if; 
 
                    when others =>
                        NULL;
                end case;
            end if;
        END IF;                
        
    end process;
    
--ila_raw_addr_DPram : ila_ipbus_fabric_rd_wr
--PORT MAP (
--  clk    => CLK_280M_i ,
--  probe0 => RAW_DPR_wr_addr_vec ,     -- 32b 
--  probe1 => RAW_DPR_rd_addr_vec ,         -- 32b  
--  probe2 => L1A_in_i_vec ,  -- 1b 
--  probe3(0) => DRP_rd_en_i,     -- 1b
--  probe4 => (others => '0' ),    -- 1b
--  probe5 => state_ID_vec,    --32b 
--    probe6 => count_vec,    -- 32b
--    probe7(0) => FIFO_wr_en_i,   -- 1b
--  probe8 => (others => '0' )  ,   -- 1b
--    probe9 => (others => '0' )    -- 1b
--);
 
end Behavioral;