cntr_L1A_generic.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;
 
entity cntr_L1A_generic is
    Port ( 
       CE   : in STD_LOGIC;
       CLK  : in STD_LOGIC;
       RST  : in STD_LOGIC;
       Q    : out STD_LOGIC_VECTOR (23 downto 0)
       );
end cntr_L1A_generic;
 
architecture Behavioral of cntr_L1A_generic is
 
    signal temp : unsigned (23 downto 0):= X"000000"  ;
--  signal terminal_cnt : unsigned (23 downto 0):= (others => '1') ;
 
begin
process (CLK)
    -- variable temp : unsigned (23 downto 0):= (others => '0') ;
    -- variable terminal_cnt : unsigned (23 downto 0):= (others => '1') ;
    begin
    if CLK'event AND CLK = '1' then
        if RST = '1' then           -- this is a synchronous reset 
            temp <= X"000000" ;              -- set counter to 1.
            -- temp := to_unsigned(1, testSignal'24);
            -- terminal_cnt <= (others => '1');   -- set terminal count value given.
        else
          if CE = '1' then
             temp <= temp + 1;                    -- else increment the value by one 
          end if;
        end if;
    end if;
    end process;
    Q <= std_logic_vector(temp) ;    -- push out new value
 
end Behavioral;