cntr_L1A_generic Entity Reference

24 bit Counter for L1A ID of process FPGA More...

Entities
Behavioral	architecture
	24 bit Counter for L1A ID of process FPGA More...

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
std_logic_arith

Ports
CE	in	STD_LOGIC
CLK	in	STD_LOGIC
RST	in	STD_LOGIC
Q	out	STD_LOGIC_VECTOR ( 23 downto 0 )

Detailed Description

24 bit Counter for L1A ID of process FPGA

This module is a 24 bit Counter for L1A ID. The counter counts when it receives either a TTC L1A or a Software L1A.
This counter is reset by either TTC ECR or Software L1A Reset.
Software L1A Reset is selected when bit 1 of resister rdout_pulse_reg is set to 1.
The rdout_pulse_reg register is pulsed, and after 1 clock cycle the contents are reset to all Zeros.

Author

Saeed Taghavi

Definition at line 16 of file cntr_L1A_generic.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/cntr_L1A_generic.vhd