Behavioral Architecture Reference

24 bit Counter for L1A ID of process FPGA More...

Processes
PROCESS_21	( CLK )

Signals
temp	unsigned ( 23 downto 0 ) := X " 000000 "

Detailed Description

24 bit Counter for L1A ID of process FPGA

This module is a 24 bit Counter for L1A ID. The counter counts when it receives either a TTC L1A or a Software L1A.
This counter is reset by either TTC ECR or Software L1A Reset.
Software L1A Reset is selected when bit 1 of resister rdout_pulse_reg is set to 1.
The rdout_pulse_reg register is pulsed, and after 1 clock cycle the contents are reset to all Zeros.

Author

Saeed Taghavi

Definition at line 26 of file cntr_L1A_generic.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/cntr_L1A_generic.vhd