fsm_TOB_double_word.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
use IEEE.NUMERIC_STD.ALL;
 
library TOB_rdout_lib;
use TOB_rdout_lib.TOB_rdout_ip_pkg.ALL;
use TOB_rdout_lib.data_type_pkg.all;
 
entity fsm_TOB_double_word is
    Port ( 
       CLK_IN               : in STD_LOGIC;
       rst_in               : in std_logic ;       
       TOB_data_in          : in STD_LOGIC_VECTOR (31 downto 0);
       double_counter_en    : out std_logic;
       DPR_wr_enable        : out STD_LOGIC
       );  
end fsm_TOB_double_word;
 
architecture Behavioral of fsm_TOB_double_word is
 
    signal  double_reg_1  : STD_LOGIC_VECTOR (31 downto 0);
    signal  double_reg_2  : STD_LOGIC_VECTOR (31 downto 0);
 
    TYPE STATE_TYPE IS (
       idle,
       ser_1,
       ser_2,
       ser_3,
       ser_4
       ) ;
  
    SIGNAL current_state : STATE_TYPE;
    signal count : integer range 0 to 7;
    signal tmp : std_logic_vector (7 downto 0);
 
begin
 
U0_clk_proc : process (CLK_IN)
    begin
        if CLK_IN'event and CLK_IN = '1' then
 
        end if;
    end process;
 
-- This FSM checks TOBs data for double identical words
 
U3_rd_XTOB_fsm : process (CLK_IN)
         
    begin
        if CLK_IN'event and CLK_IN = '1' then
            if ( rst_in = '1' )then -- RST
                current_state     <= idle ;
                double_counter_en <= '0' ;
                DPR_wr_enable     <= '0' ;
                double_reg_1      <= X"00000000";
                double_reg_2      <= X"00000000";
            else    
                double_reg_1 <= TOB_data_in;    -- latch TOB data
                double_reg_2 <= double_reg_1;   -- latch TOB data
                        
                CASE current_state is
                    when idle =>
                        double_counter_en <= '0' ;  -- signal to increment double word counter
                        DPR_wr_enable     <= '1' ;  -- signal to enable wrting into SPY RAM
                        if double_reg_1 = double_reg_2 then
                            if  double_reg_2 = X"00000000" or double_reg_2 = X"000000BC" then
                                current_state <= idle ;
                            else
                                current_state <= ser_1 ;
                            end if;
                         else
                            current_state     <= idle ;
                         end if;
                    when ser_1 =>
                            double_counter_en <= '1' ;  -- signal to increment double word counter
                            DPR_wr_enable     <= '1' ;  -- wrting into SPY RAM
                            current_state <= ser_2 ;    -- was ser_2
 
                    when ser_2 => 
                        double_counter_en <= '0' ;  -- signal to increment double word counter
                        DPR_wr_enable     <= '0' ;  -- disablee wrting into SPY RAM
                        current_state     <= ser_2 ;    -- was ser_2
                        if ( rst_in = '1' )then -- RST
                            current_state     <= idle ;
                            DPR_wr_enable     <= '1' ;  -- signal to enable wrting into SPY RAM
                        end if;
                        
                    when others =>
                        NULL;
                end case;
            end if;
        END IF;                
    end process;
 
    tmp <=  std_logic_vector(to_unsigned(count, tmp'length));
    
--U2_ila_XTOB_BCN_in : ila_ipbus_fabric_rd_wr
--PORT MAP (
--  clk    =>  CLK_IN,     
--  probe0(7 downto 0)    =>  tmp ,       -- 36b    
--  probe0(15 downto 8)   =>  (others => '0') ,       -- 36b    
--  probe0(24 downto 16)  =>  DPR_rd_addr_i (8 downto 0),       -- 36b    
--  probe0(33 downto 25)  =>  DPR_wr_addr_i (8 downto 0) ,       -- 36b    
--  probe0(35 downto 34)  =>  (others => '0') ,       -- 36b    
--  probe1    =>  (others => '0'),  -- 36b 
--  probe2(0) =>  SIPO_sync_in_i ,   -- 1b
--  probe3(0) =>  DRP_rd_en_i ,           -- 1b
--  probe4(0) =>  FIFO_wr_en_i ,   -- 1b
--  probe5    =>  (others => '0'),  -- 36b 
--  probe6    =>  (others => '0'),        -- 36b
--  probe7(0) =>  L1A_in,             -- 1b
--  probe8(0) =>  TOB_FIFO_sw_rst ,       -- 1b
--    probe9(0) =>  '0'              -- 1b
--); 
 
end Behavioral;