fsm_TOB_wr_to_FIFO.vhd File Reference

Top of fsm_TOB_wr_to_FIFO for process FPGA. More...

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Entities
fsm_TOB_wr_to_FIFO	entity
	Top of fsm_TOB_wr_to_FIFO for process FPGA. More...
Behavioral	architecture
	Top of fsm_TOB_wr_to_FIFO for process FPGA. More...

Detailed Description

Top of fsm_TOB_wr_to_FIFO for process FPGA.

This state machine is responsible for reading TOBs/XTObs and valid flags from Circular DPRAM and storing them into de-randomisation FIFO when the L1A signal is received.

It also controls multi-slice readout between 1 to 5 slices in sequence.

Author

Saeed Taghavi

Definition in file fsm_TOB_wr_to_FIFO.vhd.