tide_mark_block.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
ENTITY tide_mark_block IS
    generic (
        width  : integer := 16
        );
    PORT (
        clk_in: in std_logic;
        rst_in: in std_logic;   -- reset all packet status counters
        value_bus: in STD_LOGIC_VECTOR (width-1 downto 0);
        tide_mark_out: out STD_LOGIC_VECTOR (width-1 downto 0)
    );
END ENTITY tide_mark_block;
 
Architecture rtl of tide_mark_block is
Begin
 
    tide_mark_block: Process(clk_in)
        Variable tide_mark: unsigned(width-1 downto 0);
    Begin
        if rising_edge(clk_in) then
            if (rst_in = '1') then
                tide_mark := (Others => '0');
            elsif (tide_mark < unsigned(value_bus)) then
                tide_mark := unsigned(value_bus);
            end if;
            tide_mark_out <= std_logic_vector(tide_mark);
        end if;
    End Process tide_mark_block;
 
End rtl;