Readout_logic_top.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
Library UNISIM;
use UNISIM.vcomponents.all;
 
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
 
library TOB_rdout_lib;
use TOB_rdout_lib.data_type_pkg.all;
use TOB_rdout_lib.TOB_rdout_ip_pkg.all;
 
library ipbus_lib;
use ipbus_lib.ipbus.all;
 
library algolib;
use algolib.AlgoDataTypes.all;
 
library infrastructure_lib;
 
entity Readout_logic_top is
    Generic
        (
    FPGA_NUMBER : integer := 1
        ) ;
    Port (
       RST         : in std_logic ;
       hw_addr     : in STD_LOGIC_VECTOR(1 downto 0) ;
       ipb_rst     : in std_logic ;
       ipb_clk     : in std_logic ;
       IPb_in      : in ipb_wbus;
       IPb_out     : out ipb_rbus;
       clk_load_in   : in STD_LOGIC;
       clk_40M_rdout : in STD_LOGIC;
       clk_200M_in : in STD_LOGIC;
       clk_280M_in : in STD_LOGIC;
       clk_40M_in  : in STD_LOGIC;
       shelf_number  : in STD_LOGIC_VECTOR (3 downto 0);
       efex_slot_num  : in STD_LOGIC_VECTOR (3 downto 0);
       TOB_TXOUTCLK  : in STD_LOGIC;
       RAW_TXOUTCLK  : in STD_LOGIC;
       -- eXtended TOB data readout signals
       XTOB_eg_in             : in  AlgoXOutput;    -- array 8 x 64b words XTOB e/g
       XTOB_eg_Valid_flg_in   : in STD_LOGIC_VECTOR (7 downto 0);
       XTOB_eg_sync_in        : in STD_LOGIC;
       XTOB_tau_in            : in AlgoXOutput;        -- array 8 x 64b words XTOB tau
       XTOB_tau_Valid_flg_in  : in STD_LOGIC_VECTOR (7 downto 0);
       XTOB_tau_sync_in       : in STD_LOGIC;
       OUT_XTOB_BCN          : in std_logic_vector(6 downto 0);
       T_TOB_32b_in     : in STD_LOGIC_VECTOR (31 downto 0);
       T_TOB_sync_in    : in STD_LOGIC;
       T_TOB_valid_in   : in STD_LOGIC;
       OUT_TOB_BCN      : in std_logic_vector(6 downto 0);
       L1A_in           : in STD_LOGIC;
       ECR_in           : in STD_LOGIC;
       BCR_in            : in STD_LOGIC;
       TTC_read_all_in   : in STD_LOGIC;
       local_BCN_out     : out  STD_LOGIC_VECTOR (11 downto 0);
       TTC_L1A_ID_EXT_in : in  STD_LOGIC_VECTOR (7 downto 0);
       TTC_L1A_ID_in     : in  STD_LOGIC_VECTOR (23 downto 0);
       TTC_parity_in     : in  STD_LOGIC;
       TOB_ready_in      : in  std_logic ;
       RAW_ready_in      : in  std_logic ;
       busy_raw          : out std_logic;
       busy_tob          : out std_logic;
       TOB_out_is_char  : out STD_LOGIC;
       TOB_out          : out STD_LOGIC_VECTOR (31 downto 0);
       mgt_enable_in    : in STD_LOGIC_VECTOR (48 downto 0) ;
       RAW_data_in      : in RAW_data_227_type;
       RAW_out_is_char  : out STD_LOGIC;
       RAW_data_out     : out STD_LOGIC_VECTOR (31 downto 0)
       );
end Readout_logic_top;
 
architecture Behavioral of Readout_logic_top is
 
--************************** Register Declarations ****************************
 
    -- number of DRP locations (Slices) to read 1 to 5
    signal  DPR_locations_to_rd_i   : STD_LOGIC_VECTOR (2 downto 0) := "001" ; -- number of slices to read
    signal  trigger_slice_i         : std_logic_vector(3 downto 0) := "0000" ;   -- tigger slice number - on L1A
 
    signal  pre_ld_RAW_wr_addr_i    : STD_LOGIC_VECTOR (9 downto 0) ; -- The write address offset pre load for Circular DRPAM of RAW data
    signal  pre_ld_TOB_wr_addr_i      : STD_LOGIC_VECTOR (8 downto 0) ;
    signal  pre_ld_XTOB_eg_wr_addr_i  : STD_LOGIC_VECTOR (8 downto 0) ;
    signal  pre_ld_XTOB_tau_wr_addr_i : STD_LOGIC_VECTOR (8 downto 0) ;
    signal  RAW_data_tmp            : RAW_data_228_type;     -- array 49 x 228b input frames
--    signal  link_error_flags_i      : link_error_type;      -- array 49 x 4 bit per link
 
    signal  L1A_ID_i                : STD_LOGIC_VECTOR (23 downto 0);
    signal  L1A_ID_EXT_i            : STD_LOGIC_VECTOR (7 downto 0);
    signal  RST_i, BCR_1dly         : STD_LOGIC  ;
    signal  TTC_read_all_1dly       : STD_LOGIC  := '0' ;
    signal  rst_ECR_dbg_cntr_i      : STD_LOGIC  := '0' ;
    signal  rst_L1A_dbg_cntr_i      : STD_LOGIC  := '0' ;
 
    signal  XTOB_eg_FIFO_pFULL_THRESH_assert_i  : STD_LOGIC_VECTOR (8 downto 0) ;   -- XTOB_eg__FIFO
    signal  XTOB_eg_FIFO_pFULL_THRESH_negate_i  : STD_LOGIC_VECTOR (8 downto 0) ;   -- XTOB_eg__FIFO
    signal  XTOB_eg_FIFO_data_count_i           : STD_LOGIC_VECTOR (8 downto 0) ;   -- XTOB_eg__FIFO
    signal  XTOB_tau_FIFO_pFULL_THRESH_assert_i : STD_LOGIC_VECTOR (8 downto 0) ;   -- XTOB_tau_FIFO
    signal  XTOB_tau_FIFO_pFULL_THRESH_negate_i : STD_LOGIC_VECTOR (8 downto 0) ;   -- XTOB_tau_FIFO
    signal  XTOB_tau_FIFO_data_count_i          : STD_LOGIC_VECTOR (8 downto 0) ;   -- XTOB_tau_FIFO
 
    signal  TOB_FIFO_pFULL_THRESH_assert_i  : STD_LOGIC_VECTOR (8 downto 0) ;   -- sorted TOBs_FIFO
    signal  TOB_FIFO_pFULL_THRESH_negate_i  : STD_LOGIC_VECTOR (8 downto 0) ;   -- sorted TOBs_FIFO
    signal  TOB_FIFO_data_count_i           : STD_LOGIC_VECTOR (8 downto 0) ;   -- sorted TOBs_FIFO
    signal  tob_busy_thresh_assert_i        : STD_LOGIC_VECTOR (8 downto 0) ;   -- sorted TOBs_FIFO
    signal  tob_busy_thresh_negate_i        : STD_LOGIC_VECTOR (8 downto 0) ;   -- sorted TOBs_FIFO
    signal  TOB_Link_outpout_FIFO_pFULL_THRESH_assert_i   : STD_LOGIC_VECTOR (12 downto 0) ;   -- TOB Link o/p FIFO
    signal  TOB_Link_outpout_FIFO_pFULL_THRESH_negate_i   : STD_LOGIC_VECTOR (12 downto 0) ;   -- TOB Link o/p FIFO
    signal  TOB_Link_outpout_FIFO_rd_data_count_i         : STD_LOGIC_VECTOR (12 downto 0) ;   -- TOB Link o/p FIFO
 
    signal  RAW_FIFO_pFULL_THRESH_ASSERT_i   : STD_LOGIC_VECTOR (8 downto 0) ;   -- RAW input FIFOFIFO
    signal  RAW_FIFO_pFULL_THRESH_NEGATE_i   : STD_LOGIC_VECTOR (8 downto 0) ;   -- RAW input FIFOFIFO
 
    signal  BCN_FIFO_TOB_pFULL_THRESH_assert_i   : STD_LOGIC_VECTOR (8 downto 0) ;   -- BCN FIFO
    signal  BCN_FIFO_TOB_pFULL_THRESH_negate_i   : STD_LOGIC_VECTOR (8 downto 0) ;   -- BCN FIFO
    signal  BCN_FIFO_TOB_rd_data_count_i         : STD_LOGIC_VECTOR (8 downto 0) ;   -- BCN FIFO
    signal  BCN_FIFO_RAW_pFULL_THRESH_assert_i   : STD_LOGIC_VECTOR (8 downto 0) ;   -- BCN FIFO
    signal  BCN_FIFO_RAW_pFULL_THRESH_negate_i   : STD_LOGIC_VECTOR (8 downto 0) ;   -- BCN FIFO
    signal  BCN_FIFO_RAW_rd_data_count_i         : STD_LOGIC_VECTOR (8 downto 0) ;   -- BCN FIFO
 
    signal  Link_output_FIFO_RAW_rd_data_count_i         : STD_LOGIC_VECTOR (12 downto 0) ;   -- occupancy of RAW output link MGT FIFO
    signal  Link_output_FIFO_RAW_pfull_thresh_assert_i   : STD_LOGIC_VECTOR (12 downto 0) ;   -- link o/p FIFO
    signal  Link_output_FIFO_RAW_pfull_thresh_negate_i   : STD_LOGIC_VECTOR (12 downto 0) ;   -- link o/p FIFO
 
    signal  RAW_frame_count_i       :  STD_LOGIC_VECTOR (31 downto 0) ;      -- calo data Frame counter
    signal  RDOUT_PULSE_REG_i       : STD_LOGIC_VECTOR (31 downto 0) ;       -- pulse register in Readout block
    signal  SPY_mem_wr_addr_i       : STD_LOGIC_VECTOR (10 downto 0) ;       -- calo data SPY memory wr addr pointer
 
    signal  SPY_TOB_mem_wr_addr_i       : STD_LOGIC_VECTOR (10 downto 0) ;       -- TOB data SPY memory wr addr pointer
 
    signal  reg1 , reg2         : std_logic := '0' ;
    signal  reg3 , reg4         : std_logic := '0' ;
    signal  reg5 , reg6         : std_logic := '0' ;
    signal  reg7 , reg8         : std_logic := '0' ;
    signal  reg9 , reg10        : std_logic := '0' ;
    signal  reg11 , reg12       : std_logic := '0' ;
    signal  reg13 , reg14       : std_logic := '0' ;
    signal  reg15 , reg16       : std_logic := '0' ;
    signal  reg17 , reg18       : std_logic := '0' ;
    signal  reg19 , reg20       : std_logic := '0' ;
    signal  L1A_in_int          : std_logic := '0';
    signal  TOB_err_4b_in_i     : STD_LOGIC_VECTOR (3 downto 0);    -- 4b error flags CT + BN2 + TIE + EIE
    signal  TEST_CONTROL_REG_i  : std_logic_VECTOR (31 downto 0);       -- control register for test purposes
 
    signal  RAW_data_FIFO_flags_i   : STD_LOGIC_VECTOR (31 downto 0);
    signal  TOB_data_FIFO_flags_i   : STD_LOGIC_VECTOR (31 downto 0);
    signal  RAW_FIFO_sw_rst_i       : STD_LOGIC ;
    signal  TOB_FIFO_sw_rst_i       : STD_LOGIC ;
    signal  SPY_RAM_wr_addr_rst_i   : STD_LOGIC ;
 
    signal  XTOB_eg_512b_in_i        : AlgoXOutput;  -- i/p TOBs e/g 64b * 8
    signal  XTOB_eg_Valid_flg_in_i   : STD_LOGIC_VECTOR (7 downto 0) ;  -- i/p 8b TOB e/g has valid data
    signal  XTOB_eg_sync_in_i        : STD_LOGIC ;  -- i/p TOB e/g  sync signal
    -- XTOBs tau 64b * 8
    signal  XTOB_tau_512b_in_i       : AlgoXOutput; -- i/p TOBs tau 32b * 8
    signal  XTOB_tau_Valid_flg_in_i  : STD_LOGIC_VECTOR (7 downto 0) ; -- i/p 8b TOB tau has valid data
    signal  XTOB_tau_sync_in_i       : STD_LOGIC ;-- i/p TOB tau  sync signal
    -- Topo TOB data readout signals
    -- F1 reads e/g TOBs and F2 reads tau TOBs
    -- so same firmware in both FPGAs, use hw addr to differentiate
    signal  T_TOB_32b_in_i      : STD_LOGIC_VECTOR (31 downto 0); -- i/p sorted TOBs e/g 32b * 7 is series
    signal  T_TOB_sync_in_i     : STD_LOGIC ; -- i/p sorted TOB e/g start signal
    signal  T_TOB_valid_in_i    : STD_LOGIC ; -- i/p sorted TOB e/g write signal
    signal  TOB_type_i          : STD_LOGIC ; -- TOB Type 0 = e/g for pFPGA U1, TOB Type U1 = tau for pFPGA 2, also Zero for U3 & U4
 
    signal OUT_TOB_BCN_i        : std_logic_vector (6 downto 0); -- sorted TOB BC_ID with delay through ALGO/sorting block
    signal OUT_XTOB_BCN_i       : std_logic_vector (6 downto 0); -- sorted XTOB BC_ID with delay through ALGO/sorting block
 
    signal  ECR_1dly            : std_logic ;    -- ECR signal delayed by 1 clk
    signal  raw_rd_all_i        : std_logic ;    -- readout all raw data
    signal  read_on_err_i       : std_logic ;    -- readout raw data on error
 
    signal  TOB_ready_in_i      : std_logic ;    -- Control FPGA Ready signal internal
    signal  RAW_ready_in_i      : std_logic ;    -- Control FPGA Ready signal internal
    signal  RAW_FIFO_FULL_THRESH_ASSERT_i : STD_LOGIC_VECTOR(8 downto 0);  --  threshold to asser full flag for RAW FIFO
    signal  RAW_FIFO_FULL_THRESH_NEGATE_i : STD_LOGIC_VECTOR(8 downto 0);  --  threshold to remove full flag for RAW FIFO
    signal  RAW_FIFO_data_count_i         : STD_LOGIC_VECTOR(8 downto 0);  --  count data RAW FIFO
    signal  raw_busy_thresh_assert_i      : STD_LOGIC_VECTOR(8 downto 0);  --  count data RAW FIFO
    signal  raw_busy_thresh_negate_i      : STD_LOGIC_VECTOR(8 downto 0);  --  count data RAW FIFO
 
    signal  TOB_out_is_char_i          : std_logic ;
    signal  TOB_out_i                  : STD_LOGIC_VECTOR(31 downto 0);
 
    signal  RAW_out_is_char_i          : std_logic ;
    signal  RAW_data_out_i             : STD_LOGIC_VECTOR(31 downto 0);
 
    signal  L1A_ID_int                 : STD_LOGIC_VECTOR(31 downto 0);
    signal  L1A_ID_Event_i             : STD_LOGIC_VECTOR(31 downto 0);
    signal  local_BCN_i                : std_logic_vector(11 downto 0);
    signal  FIFO_error_flags_54b_i     : STD_LOGIC_VECTOR (53 downto 0);
    signal  busy_raw_counter_i         : STD_LOGIC_VECTOR (31 downto 0);
    signal  busy_tob_counter_i         : STD_LOGIC_VECTOR (31 downto 0);
    signal  real_time_40m_counter_i    : std_logic_vector( 31 downto 0);
    signal  busy_raw_duration_counter_i : std_logic_vector( 31 downto 0);
    signal  busy_tob_duration_counter_i : std_logic_vector( 31 downto 0);
 
    signal ipbus_out_raw_dpram_i : ipb_rbus;     -- signal going to RAW SPY DPRAM
    signal ipbus_in_raw_dpram_i  : ipb_wbus;     -- signal coming from RAW SPY DPRAM
    signal ipbus_out_tob_dpram_i : ipb_rbus;     -- signal going to TOB SPY DPRAM
    signal ipbus_in_tob_dpram_i  : ipb_wbus;     -- signal coming from TOB SPY DPRAM
 
    signal  busy_tob_i, busy_raw_i          : std_logic ;
    signal  busy_tob_tmp, busy_raw_tmp      : std_logic ;
    signal  busy_tob_1dly, busy_raw_1dly    : std_logic ;
    signal  busy_counter_rst_i  : std_logic ;
    signal  ECR_debug_counter_i : std_logic_vector( 31 downto 0);
    signal  L1A_debug_counter_i : std_logic_vector( 31 downto 0);
    signal  raw_fsm_monitor_i : std_logic_vector( 31 downto 0);
    signal  tob_fsm_monitor_i : std_logic_vector( 39 downto 0);
    signal  sync_280m_i             : std_logic;
    signal  busy_cntr_latch_i       : std_logic;
    signal  busy_reg_1, busy_reg_2  : std_logic;
    signal  tob_double_word_en_i    : std_logic;
    signal  tob_double_word_counter_i : std_logic_vector( 31 downto 0);
 
    signal  TOB_BCN_FIFO_tidemark_i   : std_logic_vector(15 downto 0);
    signal  TOB_data_FIFO_tidemark_i  : std_logic_vector(15 downto 0);
    signal  XTOB_data_FIFO_tidemark_i : std_logic_vector(15 downto 0);
    signal  TOB_LO_FIFO_tidemark_i    : std_logic_vector(15 downto 0);
 
    signal  RAW_BCN_FIFO_tidemark_i   : std_logic_vector(15 downto 0);
    signal  RAW_data_FIFO_tidemark_i  : std_logic_vector(15 downto 0);
    signal  RAW_LO_FIFO_tidemark_i    : std_logic_vector(15 downto 0);
 
    signal ttc_parity_int : std_logic := '0';
 
    signal ttc_err_history_debug: std_logic_vector(31 downto 0) := (others => '0');
    signal l1a_id_good_debug: std_logic_vector(31 downto 0) := (others => '0');
    signal l1a_id_err_debug: std_logic_vector(31 downto 0) := (others => '0');
    signal l1a_id_expected_debug: std_logic_vector(31 downto 0) := (others => '0');
    signal bcn_err_expected_debug: std_logic_vector(31 downto 0) := (others => '0');
    signal l1id_parity_err_cntr_debug: std_logic_vector(31 downto 0) := (others => '0');
    signal l1id_mismatch_cntr_debug: std_logic_vector(31 downto 0) := (others => '0');
    signal bcn_parity_err_cntr_debug: std_logic_vector(31 downto 0) := (others => '0');
    signal bcn_mismatch_cntr_debug: std_logic_vector(31 downto 0) := (others => '0');
 
--  ####### attributes  ########
    attribute TIG       : string ;
    attribute TIG of busy_tob_i    : signal is "true" ;
    attribute TIG of busy_tob_1dly : signal is "true" ;
    attribute TIG of busy_tob_tmp  : signal is "true" ;
    attribute TIG of busy_raw_i    : signal is "true" ;
    attribute TIG of busy_raw_1dly : signal is "true" ;
    attribute TIG of busy_raw_tmp  : signal is "true" ;
 
    attribute keep       : string ;
    attribute max_fanout : integer;
    attribute keep of       L1A_ID_i : signal is "true" ;
    attribute max_fanout of L1A_ID_i : signal is 40;
 
--  attribute equivalent_register_removal: string;
--  attribute equivalent_register_removal of Behavioral : architecture is "no";
 
--   #######################################
 
begin
 
    RST_i               <= RST;             -- from 40MHz MMCM lock signal
 
    busy_tob          <= busy_tob_i;                  -- TOB busy out to control FPGA
    busy_raw          <= busy_raw_i;                  -- TOB busy out to control FPGA
 
    local_BCN_out     <= local_BCN_i;
 
-- Register data out to MGT...
tob_out_reg: process(TOB_TXOUTCLK)
Begin
    if rising_edge (TOB_TXOUTCLK) then
        TOB_out_is_char  <= TOB_out_is_char_i ;
        TOB_out          <= TOB_out_i ;          -- o/p
    end if;
end process tob_out_reg;
 
raw_out_reg: process(RAW_TXOUTCLK)
Begin
    if rising_edge (RAW_TXOUTCLK) then
        RAW_out_is_char   <= RAW_out_is_char_i ;     -- Raw data valid to MGT
        RAW_data_out      <= RAW_data_out_i  ;          -- raw data 32b data to MGT
    end if;
end process raw_out_reg;
 
-- TOB Type 0 = e/g for pFPGA U1, TOB Type 1 = tau for pFPGA U2.
-- It is also Zero for pFPGA U3 and U4
TOB_type_gen : if FPGA_NUMBER = 2 generate
       TOB_type_i         <= '1' ;
    else generate
       TOB_type_i          <= '0';
    end generate TOB_type_gen;
 
-- Pipeline the TOBs and cFPGA Ready input signals by one 280 MHz clock
proc2 : process (clk_280M_in)
begin
    if rising_edge (clk_280M_in) then
        -- register the signals
        RAW_ready_in_i  <= RAW_ready_in  ;
        TOB_ready_in_i  <= TOB_ready_in ;
        -- register the TOB  data by one clock to move away from the real time circuit
        T_TOB_32b_in_i    <=  T_TOB_32b_in  ;
        T_TOB_sync_in_i   <=  T_TOB_sync_in ;
        T_TOB_valid_in_i  <=  T_TOB_valid_in   ;
        OUT_TOB_BCN_i     <=  OUT_TOB_BCN;      -- sorted TOB BC_ID with delay through ALGO/sorting block
 
        busy_tob_1dly  <= busy_tob_i;                  -- TOB busy out to control FPGA
        if  busy_tob_1dly = '0' AND busy_tob_i = '1' then
            busy_tob_tmp <= '1';    -- count number of BUSY assertions
        else
            busy_tob_tmp <= '0';
            end if;
 
        busy_raw_1dly  <= busy_raw_i;                  -- RAW busy out to control FPGA
        if  busy_raw_1dly = '0' AND busy_raw_i = '1' then
            busy_raw_tmp <= '1';    -- count number of BUSY assertions
        else
            busy_raw_tmp <= '0';
            end if;
    end if;
  end process;
 
U0_ECR_debug_counter : entity TOB_rdout_lib.cntr_generic
    generic map (
      width => 32
      )
    port map (
      CE  => ECR_1dly,  -- if a valid data, then increment
      CLK => clk_40M_in,
      RST => RST_i OR rst_ECR_dbg_cntr_i  ,
      Q   => ECR_debug_counter_i
      );
 
U0_L1A_debug_counter : entity TOB_rdout_lib.cntr_generic
    generic map (
      width => 32
      )
    port map (
      CE  => L1A_in_int,  -- if a valid data, then increment
      CLK => clk_40M_in,
      RST => RST_i OR rst_L1A_dbg_cntr_i  ,
      Q   => L1A_debug_counter_i
      );
 
U0_TOB_busy : entity TOB_rdout_lib.cntr_generic
    generic map (
      width => 32
      )
    port map (
      CE  => busy_tob_tmp,  -- if a valid data, then increment
      CLK => clk_280M_in,
      RST => RST_i OR busy_counter_rst_i  ,
      Q   => busy_tob_counter_i
      );
 
U0_RAW_busy : entity TOB_rdout_lib.cntr_generic
    generic map (
      width => 32
      )
    port map (
      CE  => busy_raw_tmp,  -- if a valid data, then increment
      CLK => clk_280M_in,
      RST => RST_i OR busy_counter_rst_i  ,
      Q   => busy_raw_counter_i
      );
 
U0_busy_tob_duration_counter : entity TOB_rdout_lib.cntr_generic
    generic map (
      width => 32
      )
    port map (
      CE  => (busy_tob_i AND sync_280m_i),  -- if a valid data, then increment
      CLK => clk_280M_in,
      RST => RST_i OR busy_counter_rst_i  ,
      Q   => busy_tob_duration_counter_i
      );
 
U0_busy_raw_duration_counter : entity TOB_rdout_lib.cntr_generic
    generic map (
      width => 32
      )
    port map (
      CE  => (busy_raw_i AND sync_280m_i),  -- if a valid data, then increment
      CLK => clk_280M_in,
      RST => RST_i OR busy_counter_rst_i  ,
      Q   => busy_raw_duration_counter_i
      );
 
U0_real_time_40m_counter : entity TOB_rdout_lib.cntr_generic
    generic map (
      width => 32
      )
    port map (
      CE  => '1',  -- if a valid data, then increment
      CLK => clk_40M_rdout,
      RST => RST_i OR busy_counter_rst_i  ,
      Q   => real_time_40m_counter_i
      );
 
U0_tob_double_word_counter : entity TOB_rdout_lib.cntr_generic
    generic map (
      width => 32
      )
    port map (
      CE  => tob_double_word_en_i,  -- if a valid data, then increment
      CLK => clk_280M_in,
      RST => RST_i OR SPY_RAM_wr_addr_rst_i  ,
      Q   => tob_double_word_counter_i
      );
 
-- TideMark Counters for BCN FIFO inside TOB/XTOB Readout
U0_tob_bcn_tidemark : entity TOB_rdout_lib.tide_mark_block
    generic map (
      width => 16
      )
    port map (
      rst_in        => RST_i OR busy_counter_rst_i  ,
      CLK_in        => clk_280M_in,
      value_bus     => "0000000" & BCN_FIFO_TOB_rd_data_count_i  ,
      tide_mark_out => TOB_BCN_FIFO_tidemark_i
      );
 
-- TideMark Counters for TOB Data FIFO inside TOB/XTOB Readout
U0_tob_data_tidemark : entity TOB_rdout_lib.tide_mark_block
    generic map (
      width => 16
      )
    port map (
      rst_in        => RST_i OR busy_counter_rst_i  ,
      CLK_in        => clk_280M_in,
      value_bus     => "0000000" & TOB_FIFO_data_count_i  ,
      tide_mark_out => TOB_data_FIFO_tidemark_i
      );
 
-- TideMark Counters for XTOB Data FIFO inside TOB/XTOB Readout
U0_xtob_data_tidemark : entity TOB_rdout_lib.tide_mark_block
    generic map (
      width => 16
      )
    port map (
      rst_in        => RST_i OR busy_counter_rst_i  ,  -- if a valid data, then increment
      CLK_in        => clk_280M_in,
      value_bus     => "0000000" & XTOB_eg_FIFO_data_count_i  ,   -- TOB & XTOB data counts are the same, use XTOB for U3 & U4
      tide_mark_out => XTOB_data_FIFO_tidemark_i
      );
 
-- TideMark Counters for TOB LO FIFO inside TOB/XTOB Readout
U0_TOB_LO_fifo_tidemark : entity TOB_rdout_lib.tide_mark_block
    generic map (
      width => 16
      )
    port map (
      rst_in        => RST_i OR busy_counter_rst_i  ,  -- if a valid data, then increment
      CLK_in        => clk_280M_in,
      value_bus     => "000" & TOB_Link_outpout_FIFO_rd_data_count_i  ,
      tide_mark_out => TOB_LO_FIFO_tidemark_i
      );
 
-- Pipeline the XTOBs input signals by one 200 MHz clock
--proc3 : process (clk_200M_in)
--begin
 
    raw_rd_all_i <= TEST_CONTROL_REG_i(0) ;                  -- software/priviledge readout all raw data
 
-- Pipeline the XTOBs input signals by one 200 MHz clock
--proc3 : process (clk_200M_in)
--begin
--    if rising_edge (clk_200M_in) then
        -- register the XTOB data by one clock to move away from the real time circuit
        XTOB_eg_512b_in_i       <= XTOB_eg_in     ;
        XTOB_eg_Valid_flg_in_i  <= XTOB_eg_Valid_flg_in ;
        XTOB_eg_sync_in_i       <= XTOB_eg_sync_in     ;
        XTOB_tau_512b_in_i      <= XTOB_tau_in     ;
        XTOB_tau_Valid_flg_in_i <= XTOB_tau_Valid_flg_in ;
        XTOB_tau_sync_in_i      <= XTOB_tau_sync_in     ;
        OUT_XTOB_BCN_i          <= OUT_XTOB_BCN;     -- sorted XTOB BC_ID with delay through ALGO/sorting block
--    end if;
--  end process;
 
-- clk reg the MUX to remove timing (L1A is seen as 8 clks instead of 7 clks)
U6_MUXF7 : process (clk_40M_in)
    begin
        if clk_40M_in'event and clk_40M_in = '1' then
           L1A_in_int   <= L1A_in ;    -- TTC L1A
           L1A_ID_EXT_i <= TTC_L1A_ID_EXT_in;   -- delay ECR_ID by 1 clocks to match the L1A_in delay of 1 ticks
           L1A_ID_i     <= TTC_L1A_ID_in;   -- delay L1ID by 1 clocks to match the L1A_in delay of 1 ticks
           ttc_parity_int <= TTC_parity_in;
        end if;
    end process;
 
-- i/p 8b Ext L1A ID from TTC input + 24b L1A ID of counter
    L1A_ID_int <= L1A_ID_EXT_i & L1A_ID_i;
 
-- TOBs_Readout Module is responsible for reading the sorted TOBs and XTOBS from outputs of Algo Block,
U0_TOBs_readout : entity TOB_rdout_lib.TOBs_rdout
    generic map(FPGA_NUMBER => FPGA_NUMBER)
    Port map (
       RST                  => RST_i,   -- i/p
       hw_addr              => hw_addr ,    -- i/p
       RST_spy_mem_wr_addr  => SPY_RAM_wr_addr_rst_i ,   -- i/p SPY memory read address reset to ZERO
       TOB_FIFO_sw_rst      => TOB_FIFO_sw_rst_i,       -- i/p TOB Readout FIFO reset Pulse under s/w control
       -- XTOBs e/g 64b * 8 as input data is 32, we have 32b * 16
       XTOB_eg_512b_in       => XTOB_eg_512b_in_i ,         -- i/p array 8 * 64b TOBs e/g
       XTOB_eg_Valid_flg_in  => XTOB_eg_Valid_flg_in_i ,    -- i/p 8b TOB e/g has valid data
       XTOB_eg_sync_in       => XTOB_eg_sync_in_i ,         -- i/p TOB e/g  sync signal
       -- XTOBs tau 64b * 8
       XTOB_tau_512b_in      => XTOB_tau_512b_in_i ,        -- i/p array 8 * 64b  TOBs tau
       XTOB_tau_Valid_flg_in => XTOB_tau_Valid_flg_in_i ,   -- i/p 8b TOB tau has valid data
       XTOB_tau_sync_in      => XTOB_tau_sync_in_i ,        -- i/p TOB tau  sync signal
       OUT_XTOB_BCN          => OUT_XTOB_BCN_i,     -- sorted XTOB BCN with delay through ALGO/sorting block
       -- TOBs data readout signals
       -- F1 reads e/g TOBs and F2 reads tau TOBs
       -- so same firmware in both FPGAs, use hw addr to differentiate
       TOBs_32b_in          =>  T_TOB_32b_in_i,        -- i/p sorted TOBs e/g 32b * 7 is series
       TOBS_sync_in         =>  T_TOB_sync_in_i,       -- i/p sorted TOB e/g start signal
       TOBs_valid_flg_in    =>  T_TOB_valid_in_i,         -- i/p sorted TOB e/g write signal
       OUT_TOB_BCN          => OUT_TOB_BCN_i,      -- sorted TOB BC_ID with delay through ALGO/sorting block
       TOB_type_in          => TOB_type_i ,
       read_on_err_in       => read_on_err_i,
       clk_40M_in           => clk_40M_in   ,       -- i/p
       clk_200M_in          => clk_200M_in   ,       -- i/p
       clk_280M_in          => clk_280M_in  ,       -- i/p
       shelf_number         => shelf_number,   -- i/p shelf address
       efex_slot_num        => efex_slot_num,  -- i/p slot address
       ipb_clk              => ipb_clk  ,           -- i/p
       TOB_TXOUTCLK         => TOB_TXOUTCLK ,       -- i/p
       L1A_in               => L1A_in_int  ,        -- input from TTC_L1A or SW_L1A
       BCN_ID_in            => local_BCN_i,            -- i/p
       L1A_ID_in            => L1A_ID_int,            -- i/p 8b Ext L1A ID from TTC input + 24b L1A ID of counter
       TOB_ready_in         => TOB_ready_in_i ,   -- i/p
 
       TOB_out_to_MGT_is_char => TOB_out_is_char_i ,  -- o/p
       TOB_out_to_MGT         => TOB_out_i ,          -- o/p
       L1A_ID_Event_out       => L1A_ID_Event_i,     -- o/p 8b L1A ID Extended + 24b L1A ID of the current event
 
       pre_ld_TOB_wr_addr       => pre_ld_TOB_wr_addr_i  ,    -- i/p latency pre load for TOB DRP wr address
       pre_ld_eg_XTOB_wr_addr   => pre_ld_XTOB_eg_wr_addr_i  ,    -- i/p latency pre load for e/g XTOB DRP wr address
       pre_ld_tau_XTOB_wr_addr  => pre_ld_XTOB_tau_wr_addr_i  ,    -- i/p latency pre load for tau XTOB DRP wr address
       cntr_load_en           => '0',      -- was cntr_load_en_i ,
       DPR_locations_to_rd    => DPR_locations_to_rd_i ,    -- i/p number of DRP locations to read 1 to 5
       trigger_slice_in       => trigger_slice_i ,          -- i/p Trigger slice number - on L1A
       TOB_data_FIFO_flags    => TOB_data_FIFO_flags_i ,    -- TOB block FIFO Flags
       -- XTOBs
       XTOB_eg_FIFO_rd_data_count        =>  XTOB_eg_FIFO_data_count_i,    -- o/p
       XTOB_eg_FIFO_pFULL_THRESH_assert  =>  XTOB_eg_FIFO_pFULL_THRESH_assert_i , -- i/p add correct register
       XTOB_eg_FIFO_pFULL_THRESH_negate  =>  XTOB_eg_FIFO_pFULL_THRESH_negate_i , -- i/p
 
       XTOB_tau_FIFO_rd_data_count       =>  XTOB_tau_FIFO_data_count_i,         -- o/p
       XTOB_tau_FIFO_pFULL_THRESH_assert =>  XTOB_tau_FIFO_pFULL_THRESH_assert_i, -- i/p
       XTOB_tau_FIFO_pFULL_THRESH_negate =>  XTOB_tau_FIFO_pFULL_THRESH_negate_i, -- i/p
       -- sorted TOBs
       T_TOB_FIFO_data_count             =>  TOB_FIFO_data_count_i,           -- o/p
       T_TOBs_FIFO_pFULL_THRESH_assert   =>  TOB_FIFO_pFULL_THRESH_assert_i,   -- i/p
       T_TOBs_FIFO_pFULL_THRESH_negate   =>  TOB_FIFO_pFULL_THRESH_negate_i,   -- i/p
       tob_busy_thresh_assert            =>  tob_busy_thresh_assert_i, -- i/p
       tob_busy_thresh_negate            =>  tob_busy_thresh_negate_i, -- i/p
 
       Link_output_FIFO_pFULL_THRESH_assert  =>  TOB_Link_outpout_FIFO_pFULL_THRESH_assert_i ,   -- i/p
       Link_output_FIFO_pFULL_THRESH_negate  =>  TOB_Link_outpout_FIFO_pFULL_THRESH_negate_i ,   -- i/p
       Link_output_FIFO_rd_data_count        =>  TOB_Link_outpout_FIFO_rd_data_count_i,  -- o/p
 
       BCN_FIFO_pFULL_THRESH_assert =>  BCN_FIFO_TOB_pFULL_THRESH_assert_i ,    -- i/p
       BCN_FIFO_pFULL_THRESH_negate =>  BCN_FIFO_TOB_pFULL_THRESH_negate_i ,    -- i/p
       BCN_FIFO_TOB_rd_data_count   =>  BCN_FIFO_TOB_rd_data_count_i ,      -- o/p
 
       SPY_TOB_mem_wr_addr    =>  SPY_TOB_mem_wr_addr_i    , -- TOB/XTOB data SPY memory wr addr pointer
       ipbus_out_tob_dpram    =>  ipbus_out_tob_dpram_i    , -- o/p signal going to TOB SPY DPRAM
       ipbus_in_tob_dpram     =>  ipbus_in_tob_dpram_i,      -- i/p signal coming from TOB SPY DPRAM
       busy_tob               =>  busy_tob_i,                -- TOB busy out to control FPGA
       sync_280m_out          =>  sync_280m_i,                -- this is 1 in 7 sync'ed to 40M clk
       tob_double_word_en     =>  tob_double_word_en_i,     -- TOB double word enable to increments double word counter
       tob_fsm_monitor        =>  tob_fsm_monitor_i
       );
 
    raw_rd_all_i <= TEST_CONTROL_REG_i(0) ;                  -- software/priviledge readout all raw data
 
-- TideMark Counters for BCN FIFO inside RAW Readout
U1_RAW_bcn_tidemark : entity TOB_rdout_lib.tide_mark_block
    generic map (
      width => 16
      )
    port map (
      rst_in        => RST_i OR busy_counter_rst_i  ,  -- if a valid data, then increment
      CLK_in        => clk_280M_in,
      value_bus     => "0000000" & BCN_FIFO_RAW_rd_data_count_i  ,
      tide_mark_out => RAW_BCN_FIFO_tidemark_i
      );
 
-- TideMark Counters for RAW Data FIFO inside RAW Readout
U1_RAW_data_tidemark : entity TOB_rdout_lib.tide_mark_block
    generic map (
      width => 16
      )
    port map (
      rst_in        => RST_i OR busy_counter_rst_i  ,  -- if a valid data, then increment
      CLK_in        => clk_280M_in,
      value_bus     => "0000000" & RAW_FIFO_data_count_i  ,
      tide_mark_out => RAW_data_FIFO_tidemark_i
      );
 
-- TideMark Counters for RAW LO FIFO inside RAW Readout
U1_RAW_LO_fifo_tidemark : entity TOB_rdout_lib.tide_mark_block
    generic map (
      width => 16
      )
    port map (
      rst_in        => RST_i OR busy_counter_rst_i  ,  -- if a valid data, then increment
      CLK_in        => clk_280M_in,
      value_bus     => "000" & Link_output_FIFO_RAW_rd_data_count_i  ,
      tide_mark_out => RAW_LO_FIFO_tidemark_i
      );
 
-- RAW_data_Readout Module is responsible for reading the RAW calorimeter data from outputs synchronisation block.
U1_RAW_readout : entity TOB_rdout_lib.RAW_data_rdout
    generic map(FPGA_NUMBER => FPGA_NUMBER)
    Port map (
       RST                 => RST_i,
       hw_addr             => hw_addr ,    -- i/p
       RST_spy_mem_wr_addr => SPY_RAM_wr_addr_rst_i ,   -- i/p SPY memory read address reset to ZERO
       RAW_FIFO_sw_rst     => RAW_FIFO_sw_rst_i ,       -- i/p this is RAW Readout FIFO reset Pulse under s/w control
       RAW_data_in         => RAW_data_in  ,          -- i/p array 49 x 227b input frames (7 x 32b)
       clk_40M_rdout       => clk_40M_in,        -- 40MHz clock for RAW data capture only
       clk_280M_in         => clk_280M_in  ,
       clk_load_in         => clk_load_in   ,
       ipb_clk             => ipb_clk  ,            -- i/p
       RAW_ready_in        => RAW_ready_in_i ,    -- i/p
       RAW_TXOUTCLK        => RAW_TXOUTCLK ,
       L1A_in              => L1A_in_int ,          -- input from TTC_L1A or SW_L1A
       BCN_ID_in           => local_BCN_i ,
       L1A_ID_in           => L1A_ID_int ,  -- i/p 8b Ext L1A ID from TTC input + 24b L1A ID of counter
--       link_error_flags_in    => link_error_flags_i ,         -- array 49 x 4 bit error per link
       raw_rd_all_in          => raw_rd_all_i ,               -- i/p  readout all raw data links
       pre_ld_wr_addr         => pre_ld_RAW_wr_addr_i,        -- The write address offset pre load for Circular DRPAM-- latency pre load for DRP wr address
       RAW_FIFO_FULL_THRESH_ASSERT   => RAW_FIFO_FULL_THRESH_ASSERT_i,
       RAW_FIFO_FULL_THRESH_NEGATE   => RAW_FIFO_FULL_THRESH_NEGATE_i,
       RAW_FIFO_data_count           => RAW_FIFO_data_count_i,
       raw_busy_thresh_assert        => raw_busy_thresh_assert_i ,
       raw_busy_thresh_negate        => raw_busy_thresh_negate_i ,
       cntr_load_en           => '0',        -- was cntr_load_en_i ,
       RAW_data_FIFO_flags    => RAW_data_FIFO_flags_i ,       -- RAW data FIFO flags
       RAW_out_to_MGT_is_char       => RAW_out_is_char_i ,     -- Raw data valid to MGT
       RAW_data_out                 => RAW_data_out_i  ,       -- raw data 32b data to MGT
       mgt_enable_in                => mgt_enable_in,          -- MGT enable signals - use to enable/disable readout on error
       frame_count                  => RAW_frame_count_i ,
       read_on_err_out              => read_on_err_i ,        -- Read RAW data on error flag
       TTC_read_all_in              => TTC_read_all_1dly,     -- TTC_Privilege Read signal input (previledge read)
       RAW_FIFO_pFULL_THRESH_ASSERT  => RAW_FIFO_pFULL_THRESH_ASSERT_i,   -- i/p
       RAW_FIFO_pFULL_THRESH_NEGATE  => RAW_FIFO_pFULL_THRESH_NEGATE_i,   -- i/p
 
       BCN_FIFO_pFULL_THRESH_assert =>  BCN_FIFO_RAW_pFULL_THRESH_assert_i ,        -- i/p
       BCN_FIFO_pFULL_THRESH_negate =>  BCN_FIFO_RAW_pFULL_THRESH_negate_i ,    -- i/p
       BCN_FIFO_RAW_rd_data_count   =>  BCN_FIFO_RAW_rd_data_count_i ,      -- o/p
 
       Link_output_FIFO_RAW_rd_data_count         => Link_output_FIFO_RAW_rd_data_count_i       ,   -- 0/p
       Link_output_FIFO_RAW_pfull_thresh_assert   => Link_output_FIFO_RAW_pfull_thresh_assert_i  ,
       Link_output_FIFO_RAW_pfull_thresh_negate   => Link_output_FIFO_RAW_pfull_thresh_negate_i ,
 
       SPY_mem_wr_addr   =>  SPY_mem_wr_addr_i    ,    -- SPY memory wr_addr (read only)
       ipbus_out_raw_dpram    =>  ipbus_out_raw_dpram_i ,    -- (o/p) signal from RAW SPY DPRAM
       ipbus_in_raw_dpram     =>  ipbus_in_raw_dpram_i,      -- (i/p) signal to RAW SPY DPRAM
       link_error_flags       =>  FIFO_error_flags_54b_i,     -- (o/p) error flags from the ERROR Flag FIFO
       busy_raw               =>  busy_raw_i,                  -- (o/p) RAW busy out to control FPGA
       raw_fsm_monitor        =>  raw_fsm_monitor_i
);
 
-- Readout_ipb_slave Module is responsible for communication with IPBus.
-- it has an interface to IPBus module, an interface to RAW Data IPBus Slave and an interface to TOB Data IPBus Slave.
U4_rdout_ipb_slave : entity TOB_rdout_lib.readout_ipb_slave
    Port map (
        ipb_rst     => ipb_rst  ,   -- i/p
        ipb_clk     => ipb_clk  ,   -- i/p
        IPb_in      => IPb_in  ,    -- i/p
        IPb_out     => IPb_out ,    -- o/p
        L1A_ID_Event  => L1A_ID_Event_i ,   -- i/p 32b L1A ID of current event
        L1A_ID        => L1A_ID_int ,     -- i/p 8b Ext L1A ID from TTC input + 24b L1A ID of counter
        BCN_in        => local_BCN_i ,    -- i/p
        -- TOB/XTOB
        TOB_WR_ADDR_OFFSET               =>  pre_ld_TOB_wr_addr_i,          -- o/p
        XTOB_EG_WR_ADDR_OFFSET           =>  pre_ld_XTOB_eg_wr_addr_i,          -- o/p
        XTOB_TAU_WR_ADDR_OFFSET          =>  pre_ld_XTOB_tau_wr_addr_i,          -- o/p
        TOB_SLICES_TO_RD                 =>  DPR_locations_to_rd_i,         -- o/p number of slices to read
        trigger_slice                    =>  trigger_slice_i,         -- o/p Trigger slice number - on L1A
        BCN_FIFO_TOB_rd_data_count       =>  TOB_BCN_FIFO_tidemark_i & "0000000" & BCN_FIFO_TOB_rd_data_count_i    ,    -- i/p
        BCN_FIFO_TOB_pFULL_THRESH_ASSERT =>  BCN_FIFO_TOB_pFULL_THRESH_assert_i, -- o/p
        BCN_FIFO_TOB_pFULL_THRESH_NEGATE =>  BCN_FIFO_TOB_pFULL_THRESH_negate_i, -- o/p
        TOB_FIFO_pFULL_THRESH_ASSERT      =>  TOB_FIFO_pFULL_THRESH_assert_i, -- o/p
        TOB_FIFO_pFULL_THRESH_NEGATE      =>  TOB_FIFO_pFULL_THRESH_negate_i, -- o/p
        TOB_FIFO_DATA_COUNT               =>  XTOB_data_FIFO_tidemark_i & "0000000" & TOB_FIFO_data_count_i    ,         -- i/p
        tob_busy_thresh_assert            =>  tob_busy_thresh_assert_i, -- i/p
        tob_busy_thresh_negate            =>  tob_busy_thresh_negate_i, -- i/p
        XTOB_EG_FIFO_pFULL_THRESH_ASSERT  =>  XTOB_eg_FIFO_pFULL_THRESH_assert_i, -- o/p
        XTOB_EG_FIFO_pFULL_THRESH_NEGATE  =>  XTOB_eg_FIFO_pFULL_THRESH_negate_i, -- o/p
        XTOB_EG_FIFO_DATA_COUNT           =>  XTOB_data_FIFO_tidemark_i & "0000000" & XTOB_eg_FIFO_data_count_i    ,         -- i/p
        XTOB_TAU_FIFO_pFULL_THRESH_ASSERT =>  XTOB_tau_FIFO_pFULL_THRESH_assert_i,    -- o/p
        XTOB_TAU_FIFO_pFULL_THRESH_NEGATE =>  XTOB_tau_FIFO_pFULL_THRESH_negate_i,    -- o/p
        XTOB_TAU_FIFO_DATA_COUNT          =>  XTOB_data_FIFO_tidemark_i & "0000000" & XTOB_tau_FIFO_data_count_i    ,            -- i/p
        TOB_Link_output_FIFO_pFULL_THRESH_ASSERT  =>  TOB_Link_outpout_FIFO_pFULL_THRESH_assert_i,-- o/p
        TOB_Link_output_FIFO_pFULL_THRESH_NEGATE  =>  TOB_Link_outpout_FIFO_pFULL_THRESH_negate_i,-- o/p
        TOB_LINK_OUTPUT_FIFO_RD_DATA_COUNT        =>  TOB_LO_FIFO_tidemark_i  & "000" & TOB_Link_outpout_FIFO_rd_data_count_i     ,     -- i/p
        TOB_data_FIFO_flags             =>  TOB_data_FIFO_flags_i ,      -- i/p 12 bits
        tob_fsm_monitor                 =>  tob_fsm_monitor_i,
 
        -- RAW calorimeter data                      =>  ,
        RAW_WR_ADDR_OFFSET            =>  pre_ld_RAW_wr_addr_i,          -- o/p
        RAW_FIFO_pFULL_THRESH_ASSERT  =>  RAW_FIFO_pFULL_THRESH_ASSERT_i,    -- o/p
        RAW_FIFO_pFULL_THRESH_NEGATE  =>  RAW_FIFO_pFULL_THRESH_NEGATE_i,    -- o/p
 
        BCN_FIFO_RAW_pFULL_THRESH_assert  =>  BCN_FIFO_RAW_pFULL_THRESH_assert_i ,   -- o/p
        BCN_FIFO_RAW_pFULL_THRESH_negate  =>  BCN_FIFO_RAW_pFULL_THRESH_negate_i ,   -- o/p
        BCN_FIFO_RAW_rd_data_count        =>  RAW_BCN_FIFO_tidemark_i & "0000000" & BCN_FIFO_RAW_rd_data_count_i     ,      -- i/p
        Link_output_FIFO_RAW_pfull_thresh_assert   =>  Link_output_FIFO_RAW_pfull_thresh_assert_i  ,    -- o/p
        Link_output_FIFO_RAW_pfull_thresh_negate   =>  Link_output_FIFO_RAW_pfull_thresh_negate_i  ,    -- o/p
        Link_output_FIFO_RAW_rd_data_count        =>  RAW_LO_FIFO_tidemark_i & "000" & Link_output_FIFO_RAW_rd_data_count_i           ,  -- i/p
        RAW_FIFO_FULL_THRESH_ASSERT   => RAW_FIFO_FULL_THRESH_ASSERT_i,   -- o/p
        RAW_FIFO_FULL_THRESH_NEGATE   => RAW_FIFO_FULL_THRESH_NEGATE_i,   -- o/p
        RAW_FIFO_data_count           => RAW_data_FIFO_tidemark_i & "0000000" & RAW_FIFO_data_count_i    ,   -- i/p
        raw_busy_thresh_assert        => raw_busy_thresh_assert_i ,
        raw_busy_thresh_negate        => raw_busy_thresh_negate_i ,
        RAW_frame_count        =>  RAW_frame_count_i ,
        RAW_data_FIFO_flags    =>  RAW_data_FIFO_flags_i ,    -- (i/p) 32 bits
        raw_fsm_monitor        =>  raw_fsm_monitor_i,
        SPY_TOB_mem_wr_addr    =>  SPY_TOB_mem_wr_addr_i ,    -- (i/p) TOB/XTOB data SPY memory wr addr pointer
        ipbus_out_tob_dpram    =>  ipbus_in_tob_dpram_i ,     -- (o/p) signal to TOB SPY DPRAM
        ipbus_in_tob_dpram     =>  ipbus_out_tob_dpram_i ,    -- (i/p) signal from TOB SPY DPRAM
        RDOUT_PULSE_REG        =>  RDOUT_PULSE_REG_i ,        -- (o/p) pulsed register
        SPY_RAW_mem_wr_addr    =>  SPY_mem_wr_addr_i    ,     -- (o/p) RAW calo data SPY memory wr addr pointer
        ipbus_out_raw_dpram    =>  ipbus_in_raw_dpram_i ,     -- (o/p) signal to RAW SPY DPRAM
        ipbus_in_raw_dpram     =>  ipbus_out_raw_dpram_i ,    -- (i/p) signal from RAW SPY DPRAM
        TEST_CONTROL_REG       =>  TEST_CONTROL_REG_i,        -- (o/p) control register for testing purposes
        link_error_flags       =>  FIFO_error_flags_54b_i,    -- (i/p) error flags from the ERROR Flag FIFO
        busy_raw_counter       =>  busy_raw_counter_i,        -- (i/p) Number of RAW Readout BUSY assertions
        busy_tob_counter       =>  busy_tob_counter_i,        -- (i/p) Number of TOB Readout BUSY assertions
        busy_raw_duration_counter =>  busy_raw_duration_counter_i,  -- (i/p) Number of 40M clocks RAW Readout BUSY is asserted
        busy_tob_duration_counter =>  busy_tob_duration_counter_i,  -- (i/p) Number of 40M clocks TOB Readout BUSY is asserted
        ECR_debug_counter      =>  ECR_debug_counter_i,       -- ECR_debug_counter
        L1A_debug_counter      =>  L1A_debug_counter_i,        -- L1A_debug_counter
        real_time_40m_counter  =>  real_time_40m_counter_i,        -- Number of 40M clocks
        tob_double_word_counter  =>  tob_double_word_counter_i,     -- Number of identical TOB double words
 
        -- Parity error output
        ttc_err_history_debug => ttc_err_history_debug,
        l1a_id_good_debug => l1a_id_good_debug,
        l1a_id_err_debug => l1a_id_err_debug,
        l1a_id_expected_debug => l1a_id_expected_debug,
        bcn_err_expected_debug => bcn_err_expected_debug,
        l1id_parity_err_cntr_debug => l1id_parity_err_cntr_debug,
        l1id_mismatch_cntr_debug => l1id_mismatch_cntr_debug,
        bcn_parity_err_cntr_debug => bcn_parity_err_cntr_debug,
        bcn_mismatch_cntr_debug => bcn_mismatch_cntr_debug
        );
 
-- U5_bcn_counter process is responsible for generating BCN = Bunch Crossing Number.
-- The orbit is 3564 long, from 0 to 3563.
-- Cunch Crossing counter is set to 1 upon receiving TTC BCR
U5_bcn_counter : process(clk_40M_in)
    variable bcn_count : unsigned (11 downto 0) := (others => '0');
  begin
 
    if rising_edge (clk_40M_in) then
    -- register TTC input signals to keep them in synch
      BCR_1dly      <= BCR_in;  -- delay by another clk to match the delay on L1A_i
      ECR_1dly      <= ECR_in; -- delay by 1 clk to match L1A delay
      TTC_read_all_1dly <= TTC_read_all_in; -- delay by 1 clk to match L1A delay
 
      if BCR_in = '1' then
        bcn_count := ("000000000000");
      else
        if bcn_count = 3563 then
          bcn_count := (others => '0');
        else
          bcn_count := bcn_count + 1;
        end if;
      end if;
      local_BCN_i <= std_logic_vector(bcn_count);
    end if;
  end process;
 
-- RAW_FIFO_sw_rst process generates a Software Reset to 49 RAW FIFO blocks which store the input calorimeter data.
-- RAW FIFO Software Reset is selected when bit 2 of resister rdout_pulse_reg is set 1o 1
-- The rdout_pulse_reg register is pulsed, and after 1 clock cycle the contents are reset to all Zeros.
U9_RAW_FIFO_sw_rst : process (clk_40M_rdout)
    begin
        if clk_40M_rdout'event and clk_40M_rdout = '1' then
            reg7    <= RDOUT_PULSE_REG_i(2) ;   -- this is RAW Data FIFO Software Reset
            reg8    <= reg7 ;
            RAW_FIFO_sw_rst_i    <= reg7 AND (NOT reg8) ;
        end if;
    end process;
 
-- TOB_FIFO_sw_rst process generates a Software Reset to 3 FIFO blocks which store TOB and XTOB data.
-- TOB FIFO Software Reset is selected when bit 3 of resister rdout_pulse_reg is set 1o 1
-- The rdout_pulse_reg register is pulsed, and after 1 clock cycle the contents are reset to all Zeros.
U10_TOB_FIFO_sw_rst : process (clk_40M_rdout)
    begin
        if clk_40M_rdout'event and clk_40M_rdout = '1' then
            reg9    <= RDOUT_PULSE_REG_i(3) ;   -- this is TOB/XTOB Data FIFO Software Reset
            reg10    <= reg9 ;
            TOB_FIFO_sw_rst_i    <= reg9 AND (NOT reg10) ;
        end if;
    end process;
 
-- SPY_RAM_wr_addr_rst process generates a Software Reset to reset the write address of Spy Memoreis to ZERO.
-- This reset is applied to both RAW and TOB/XTOB Spy Memories.
-- SPY_RAM_wr_addr_rst is selected when bit 5 of resister rdout_pulse_reg is set 1o 1
-- The rdout_pulse_reg register is pulsed, and after 1 clock cycle the contents are reset to all Zeros.
U12_SPY_RAM_wr_addr_rst : process (clk_40M_rdout)
    begin
        if clk_40M_rdout'event and clk_40M_rdout = '1' then
            reg11    <= RDOUT_PULSE_REG_i(5) ;   -- this is SPY Memory Write Address Software Reset
            reg12    <= reg11 ;
            SPY_RAM_wr_addr_rst_i    <= reg11 AND (NOT reg12) ;
        end if;
    end process;
 
-- Reset signal to clear BUSY counters for RAW and TOB data readout
U13_busy_counter_rst : process (clk_40M_rdout)
    begin
        if clk_40M_rdout'event and clk_40M_rdout = '1' then
            reg13    <= RDOUT_PULSE_REG_i(6) ;   -- this is SPY Memory Write Address Software Reset
            reg14    <= reg13 ;
            busy_counter_rst_i    <= reg13 AND (NOT reg14) ;
        end if;
    end process;
 
U14_rst_ECR_dbg_cntr : process (clk_40M_rdout)
    begin
        if clk_40M_rdout'event and clk_40M_rdout = '1' then
            reg15    <= RDOUT_PULSE_REG_i(7) ;   -- Reset ECR Debug Counter
            reg16    <= reg15 ;
            rst_ECR_dbg_cntr_i    <= reg15 AND (NOT reg16) ;
        end if;
    end process;
 
-- Reset signal to clear BUSY counters for RAW and TOB data readout
U15_rst_L1A_dbg_cntr : process (clk_40M_rdout)
    begin
        if clk_40M_rdout'event and clk_40M_rdout = '1' then
            reg17    <= RDOUT_PULSE_REG_i(8) ;   -- Reset L1A Debug Counter
            reg18    <= reg17 ;
            rst_L1A_dbg_cntr_i    <= reg17 AND (NOT reg18) ;
        end if;
    end process;
 
-- Reset signal to clear BUSY counters for RAW and TOB data readout
U16_latch_busy_cntr : process (clk_40M_rdout)
    begin
        if clk_40M_rdout'event and clk_40M_rdout = '1' then
            reg19    <= RDOUT_PULSE_REG_i(9) ;   -- Reset L1A Debug Counter
            reg20    <= reg19 ;
            busy_cntr_latch_i    <= reg19 AND (NOT reg20) ;
        end if;
    end process;
 
U17_bcn_l1a_valid_checker : entity infrastructure_lib.bcn_l1a_valid_checker
    Port map(
        clk_40_i => clk_40M_in,
        rst_i => rst_L1A_dbg_cntr_i,
        l1a_id_ext_i => L1A_ID_int,
        l1a_in_i => L1A_in_int,
        ecr_in_i => ECR_1dly,
        bcn_id_lcl_i => local_BCN_i,
        ttc_parity_i => TTC_parity_int,
 
        err_history_o => ttc_err_history_debug,
        l1a_id_good_o => l1a_id_good_debug,
        l1a_id_err_o => l1a_id_err_debug,
        l1a_id_expected_o => l1a_id_expected_debug,
        bcn_err_expected_o => bcn_err_expected_debug,
        l1id_parity_err_cntr_o => l1id_parity_err_cntr_debug,
        l1id_mismatch_cntr_o => l1id_mismatch_cntr_debug,
        bcn_parity_err_cntr_o => bcn_parity_err_cntr_debug,
        bcn_mismatch_cntr_o => bcn_mismatch_cntr_debug
    );
end Behavioral;