bcn_l1a_valid_checker Entity Reference

Observes BCN ID, L1A ID, and parity bits. More...

Inheritance diagram for bcn_l1a_valid_checker:

Entities
rtl	architecture
	Observes BCN ID, L1A ID, and parity bits. More...

Libraries
ieee
TOB_rdout_lib
infrastructure_lib

Use Clauses
std_logic_1164
numeric_std

Generics
ILA_ENABLED	std_logic := ' 0 '

Ports
clk_40_i	in	std_logic
rst_i	in	std_logic
l1a_id_ext_i	in	std_logic_vector ( 31 downto 0 )
l1a_in_i	in	std_logic
ecr_in_i	in	std_logic
bcn_id_lcl_i	in	std_logic_vector ( 11 downto 0 )
ttc_parity_i	in	std_logic
err_history_o	out	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
l1a_id_good_o	out	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
l1a_id_err_o	out	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
l1a_id_expected_o	out	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
bcn_err_expected_o	out	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
l1id_parity_err_cntr_o	out	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
l1id_mismatch_cntr_o	out	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
bcn_parity_err_cntr_o	out	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
bcn_mismatch_cntr_o	out	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Detailed Description

Observes BCN ID, L1A ID, and parity bits.

When L1A_in = '1', L1A_ID_ext => L1A_ID; When L1A_in = '0', L1A_ID_ext(11 downto 0) => BCN_ID; So when L1A_in is active, check behaviour of L1A_ID and the respective parity bits When L1A_in is not active, check behaviour of L1A_ID, (local) BCN_ID, and parity bits

Author

Geoffrey Betts

Definition at line 19 of file bcn_l1a_valid_checker.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Inter_Connection/bcn_l1a_valid_checker.vhd