rtl Architecture Reference

Observes BCN ID, L1A ID, and parity bits. More...

Processes
l1id_next_block	( clk_40_i )
debug_output	( clk_40_i )

Components
ila_1

Signals
probe_o	std_logic_vector ( 34 downto 0 ) := ( others = > ' 0 ' )
l1id_next	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
bcn_err_trigger	std_logic
bcn_mismatch_trigger	std_logic
l1id_err_trigger	std_logic
l1id_mismatch_trigger	std_logic
parity12	std_logic
parity32	std_logic

Instantiations
ttc_parity_calc	ttc_parity <Entity ttc_parity>
l1id_parity_err_cntr_block	cntr_generic <Entity cntr_generic>
l1id_mismatch_cntr_block	cntr_generic <Entity cntr_generic>
bcn_parity_err_cntr_block	cntr_generic <Entity cntr_generic>
bcn_mismatch_cntr_block	cntr_generic <Entity cntr_generic>
debug_bcn_l1a_parity	ila_1

Detailed Description

Observes BCN ID, L1A ID, and parity bits.

When L1A_in = '1', L1A_ID_ext => L1A_ID; When L1A_in = '0', L1A_ID_ext(11 downto 0) => BCN_ID; So when L1A_in is active, check behaviour of L1A_ID and the respective parity bits When L1A_in is not active, check behaviour of L1A_ID, (local) BCN_ID, and parity bits

Author

Geoffrey Betts

Definition at line 46 of file bcn_l1a_valid_checker.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Inter_Connection/bcn_l1a_valid_checker.vhd