Top Level of Readout Logic for process FPGA. More...

Processes
tob_out_reg	( TOB_TXOUTCLK )
raw_out_reg	( RAW_TXOUTCLK )
proc2	( clk_280M_in )
U6_MUXF7	( clk_40M_in )
U5_bcn_counter	( clk_40M_in )
U9_RAW_FIFO_sw_rst	( clk_40M_rdout )
U10_TOB_FIFO_sw_rst	( clk_40M_rdout )
U12_SPY_RAM_wr_addr_rst	( clk_40M_rdout )
U13_busy_counter_rst	( clk_40M_rdout )
U14_rst_ECR_dbg_cntr	( clk_40M_rdout )
U15_rst_L1A_dbg_cntr	( clk_40M_rdout )
U16_latch_busy_cntr	( clk_40M_rdout )

Signals
DPR_locations_to_rd_i	STD_LOGIC_VECTOR ( 2 downto 0 ) := " 001 "
trigger_slice_i	std_logic_vector ( 3 downto 0 ) := " 0000 "
pre_ld_RAW_wr_addr_i	STD_LOGIC_VECTOR ( 9 downto 0 )
pre_ld_TOB_wr_addr_i	STD_LOGIC_VECTOR ( 8 downto 0 )
pre_ld_XTOB_eg_wr_addr_i	STD_LOGIC_VECTOR ( 8 downto 0 )
pre_ld_XTOB_tau_wr_addr_i	STD_LOGIC_VECTOR ( 8 downto 0 )
RAW_data_tmp	RAW_data_228_type
L1A_ID_i	STD_LOGIC_VECTOR ( 23 downto 0 )
L1A_ID_EXT_i	STD_LOGIC_VECTOR ( 7 downto 0 )
RST_i	STD_LOGIC
BCR_1dly	STD_LOGIC
TTC_read_all_1dly	STD_LOGIC := ' 0 '
rst_ECR_dbg_cntr_i	STD_LOGIC := ' 0 '
rst_L1A_dbg_cntr_i	STD_LOGIC := ' 0 '
XTOB_eg_FIFO_pFULL_THRESH_assert_i	STD_LOGIC_VECTOR ( 8 downto 0 )
XTOB_eg_FIFO_pFULL_THRESH_negate_i	STD_LOGIC_VECTOR ( 8 downto 0 )
XTOB_eg_FIFO_data_count_i	STD_LOGIC_VECTOR ( 8 downto 0 )
XTOB_tau_FIFO_pFULL_THRESH_assert_i	STD_LOGIC_VECTOR ( 8 downto 0 )
XTOB_tau_FIFO_pFULL_THRESH_negate_i	STD_LOGIC_VECTOR ( 8 downto 0 )
XTOB_tau_FIFO_data_count_i	STD_LOGIC_VECTOR ( 8 downto 0 )
TOB_FIFO_pFULL_THRESH_assert_i	STD_LOGIC_VECTOR ( 8 downto 0 )
TOB_FIFO_pFULL_THRESH_negate_i	STD_LOGIC_VECTOR ( 8 downto 0 )
TOB_FIFO_data_count_i	STD_LOGIC_VECTOR ( 8 downto 0 )
tob_busy_thresh_assert_i	STD_LOGIC_VECTOR ( 8 downto 0 )
tob_busy_thresh_negate_i	STD_LOGIC_VECTOR ( 8 downto 0 )
TOB_Link_outpout_FIFO_pFULL_THRESH_assert_i	STD_LOGIC_VECTOR ( 12 downto 0 )
TOB_Link_outpout_FIFO_pFULL_THRESH_negate_i	STD_LOGIC_VECTOR ( 12 downto 0 )
TOB_Link_outpout_FIFO_rd_data_count_i	STD_LOGIC_VECTOR ( 12 downto 0 )
RAW_FIFO_pFULL_THRESH_ASSERT_i	STD_LOGIC_VECTOR ( 8 downto 0 )
RAW_FIFO_pFULL_THRESH_NEGATE_i	STD_LOGIC_VECTOR ( 8 downto 0 )
BCN_FIFO_TOB_pFULL_THRESH_assert_i	STD_LOGIC_VECTOR ( 8 downto 0 )
BCN_FIFO_TOB_pFULL_THRESH_negate_i	STD_LOGIC_VECTOR ( 8 downto 0 )
BCN_FIFO_TOB_rd_data_count_i	STD_LOGIC_VECTOR ( 8 downto 0 )
BCN_FIFO_RAW_pFULL_THRESH_assert_i	STD_LOGIC_VECTOR ( 8 downto 0 )
BCN_FIFO_RAW_pFULL_THRESH_negate_i	STD_LOGIC_VECTOR ( 8 downto 0 )
BCN_FIFO_RAW_rd_data_count_i	STD_LOGIC_VECTOR ( 8 downto 0 )
Link_output_FIFO_RAW_rd_data_count_i	STD_LOGIC_VECTOR ( 12 downto 0 )
Link_output_FIFO_RAW_pfull_thresh_assert_i	STD_LOGIC_VECTOR ( 12 downto 0 )
Link_output_FIFO_RAW_pfull_thresh_negate_i	STD_LOGIC_VECTOR ( 12 downto 0 )
RAW_frame_count_i	STD_LOGIC_VECTOR ( 31 downto 0 )
RDOUT_PULSE_REG_i	STD_LOGIC_VECTOR ( 31 downto 0 )
SPY_mem_wr_addr_i	STD_LOGIC_VECTOR ( 10 downto 0 )
SPY_TOB_mem_wr_addr_i	STD_LOGIC_VECTOR ( 10 downto 0 )
reg1	std_logic := ' 0 '
reg2	std_logic := ' 0 '
reg3	std_logic := ' 0 '
reg4	std_logic := ' 0 '
reg5	std_logic := ' 0 '
reg6	std_logic := ' 0 '
reg7	std_logic := ' 0 '
reg8	std_logic := ' 0 '
reg9	std_logic := ' 0 '
reg10	std_logic := ' 0 '
reg11	std_logic := ' 0 '
reg12	std_logic := ' 0 '
reg13	std_logic := ' 0 '
reg14	std_logic := ' 0 '
reg15	std_logic := ' 0 '
reg16	std_logic := ' 0 '
reg17	std_logic := ' 0 '
reg18	std_logic := ' 0 '
reg19	std_logic := ' 0 '
reg20	std_logic := ' 0 '
L1A_in_int	std_logic := ' 0 '
TOB_err_4b_in_i	STD_LOGIC_VECTOR ( 3 downto 0 )
TEST_CONTROL_REG_i	std_logic_VECTOR ( 31 downto 0 )
RAW_data_FIFO_flags_i	STD_LOGIC_VECTOR ( 31 downto 0 )
TOB_data_FIFO_flags_i	STD_LOGIC_VECTOR ( 31 downto 0 )
RAW_FIFO_sw_rst_i	STD_LOGIC
TOB_FIFO_sw_rst_i	STD_LOGIC
SPY_RAM_wr_addr_rst_i	STD_LOGIC
XTOB_eg_512b_in_i	AlgoXOutput
XTOB_eg_Valid_flg_in_i	STD_LOGIC_VECTOR ( 7 downto 0 )
XTOB_eg_sync_in_i	STD_LOGIC
XTOB_tau_512b_in_i	AlgoXOutput
XTOB_tau_Valid_flg_in_i	STD_LOGIC_VECTOR ( 7 downto 0 )
XTOB_tau_sync_in_i	STD_LOGIC
T_TOB_32b_in_i	STD_LOGIC_VECTOR ( 31 downto 0 )
T_TOB_sync_in_i	STD_LOGIC
T_TOB_valid_in_i	STD_LOGIC
TOB_type_i	STD_LOGIC
OUT_TOB_BCN_i	std_logic_vector ( 6 downto 0 )
OUT_XTOB_BCN_i	std_logic_vector ( 6 downto 0 )
ECR_1dly	std_logic
raw_rd_all_i	std_logic
read_on_err_i	std_logic
TOB_ready_in_i	std_logic
RAW_ready_in_i	std_logic
RAW_FIFO_FULL_THRESH_ASSERT_i	STD_LOGIC_VECTOR ( 8 downto 0 )
RAW_FIFO_FULL_THRESH_NEGATE_i	STD_LOGIC_VECTOR ( 8 downto 0 )
RAW_FIFO_data_count_i	STD_LOGIC_VECTOR ( 8 downto 0 )
raw_busy_thresh_assert_i	STD_LOGIC_VECTOR ( 8 downto 0 )
raw_busy_thresh_negate_i	STD_LOGIC_VECTOR ( 8 downto 0 )
TOB_out_is_char_i	std_logic
TOB_out_i	STD_LOGIC_VECTOR ( 31 downto 0 )
RAW_out_is_char_i	std_logic
RAW_data_out_i	STD_LOGIC_VECTOR ( 31 downto 0 )
L1A_ID_int	STD_LOGIC_VECTOR ( 31 downto 0 )
L1A_ID_Event_i	STD_LOGIC_VECTOR ( 31 downto 0 )
local_BCN_i	std_logic_vector ( 11 downto 0 )
FIFO_error_flags_54b_i	STD_LOGIC_VECTOR ( 53 downto 0 )
busy_raw_counter_i	STD_LOGIC_VECTOR ( 31 downto 0 )
busy_tob_counter_i	STD_LOGIC_VECTOR ( 31 downto 0 )
real_time_40m_counter_i	std_logic_vector ( 31 downto 0 )
busy_raw_duration_counter_i	std_logic_vector ( 31 downto 0 )
busy_tob_duration_counter_i	std_logic_vector ( 31 downto 0 )
ipbus_out_raw_dpram_i	ipb_rbus
ipbus_in_raw_dpram_i	ipb_wbus
ipbus_out_tob_dpram_i	ipb_rbus
ipbus_in_tob_dpram_i	ipb_wbus
busy_tob_i	std_logic
busy_raw_i	std_logic
busy_tob_tmp	std_logic
busy_raw_tmp	std_logic
busy_tob_1dly	std_logic
busy_raw_1dly	std_logic
busy_counter_rst_i	std_logic
ECR_debug_counter_i	std_logic_vector ( 31 downto 0 )
L1A_debug_counter_i	std_logic_vector ( 31 downto 0 )
raw_fsm_monitor_i	std_logic_vector ( 31 downto 0 )
tob_fsm_monitor_i	std_logic_vector ( 39 downto 0 )
sync_280m_i	std_logic
busy_cntr_latch_i	std_logic
busy_reg_1	std_logic
busy_reg_2	std_logic
tob_double_word_en_i	std_logic
tob_double_word_counter_i	std_logic_vector ( 31 downto 0 )
TOB_BCN_FIFO_tidemark_i	std_logic_vector ( 15 downto 0 )
TOB_data_FIFO_tidemark_i	std_logic_vector ( 15 downto 0 )
XTOB_data_FIFO_tidemark_i	std_logic_vector ( 15 downto 0 )
TOB_LO_FIFO_tidemark_i	std_logic_vector ( 15 downto 0 )
RAW_BCN_FIFO_tidemark_i	std_logic_vector ( 15 downto 0 )
RAW_data_FIFO_tidemark_i	std_logic_vector ( 15 downto 0 )
RAW_LO_FIFO_tidemark_i	std_logic_vector ( 15 downto 0 )
ttc_parity_int	std_logic := ' 0 '
ttc_err_history_debug	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
l1a_id_good_debug	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
l1a_id_err_debug	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
l1a_id_expected_debug	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
bcn_err_expected_debug	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
l1id_parity_err_cntr_debug	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
l1id_mismatch_cntr_debug	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
bcn_parity_err_cntr_debug	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
bcn_mismatch_cntr_debug	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )

Attributes
TIG	string
TIG	signal is " true "
keep	string
max_fanout	integer
keep	signal is " true "
max_fanout	signal is 40

Instantiations
u0_ecr_debug_counter	cntr_generic <Entity cntr_generic>
u0_l1a_debug_counter	cntr_generic <Entity cntr_generic>
u0_tob_busy	cntr_generic <Entity cntr_generic>
u0_raw_busy	cntr_generic <Entity cntr_generic>
u0_busy_tob_duration_counter	cntr_generic <Entity cntr_generic>
u0_busy_raw_duration_counter	cntr_generic <Entity cntr_generic>
u0_real_time_40m_counter	cntr_generic <Entity cntr_generic>
u0_tob_double_word_counter	cntr_generic <Entity cntr_generic>
u0_tob_bcn_tidemark	tide_mark_block <Entity tide_mark_block>
u0_tob_data_tidemark	tide_mark_block <Entity tide_mark_block>
u0_xtob_data_tidemark	tide_mark_block <Entity tide_mark_block>
u0_tob_lo_fifo_tidemark	tide_mark_block <Entity tide_mark_block>
u0_tobs_readout	TOBs_rdout <Entity TOBs_rdout>
u1_raw_bcn_tidemark	tide_mark_block <Entity tide_mark_block>
u1_raw_data_tidemark	tide_mark_block <Entity tide_mark_block>
u1_raw_lo_fifo_tidemark	tide_mark_block <Entity tide_mark_block>
u1_raw_readout	RAW_data_rdout <Entity RAW_data_rdout>
u4_rdout_ipb_slave	readout_ipb_slave <Entity readout_ipb_slave>
u17_bcn_l1a_valid_checker	bcn_l1a_valid_checker <Entity bcn_l1a_valid_checker>

Detailed Description

Top Level of Readout Logic for process FPGA.

This is the top module of the Readout Logic The inputs are:

Calorimeter data extracted from the real-time path at the input to the algorithm block
XTOBs for tau or e/g data from the real-time path at the output of the algorithm block
Merged Sorted TOBs from the real-time path at the output of the merging block

The Readout output is two streams of 32b data and consists of:

RAW Calorimeter data
Merged Sorted TOBs & local XTOBs as defined in eFEX data format document.

Two streams of 32b data is fed to two MGTs through Link Output FIFOs for tranfer to Control FPGA

Readout Logic Block Diagram

This block consists of four submodules: Submodule 1 : TOBs_Readout Submodule 2 : RAW_data_Readout Submodule 3 : readout_ipb_slave Submodule 4 : L1A counter

TOBs_Readout Module is responsible for reading the merged sorted TOBs and local XTOBS from outputs of Algo Block, and creating a full events, storing only valid TOBs and XTOBs.

The events are stored in Link Output FIFO ready to be sent to Control FPGA via an MGT link.
Process FPGA 1 reads e/g TOBs and Process FPGA 2 reads tau TOBs, so same firmware in both FPGAs, use FPGA_NUMBER generic to differentiate.

RAW_data_Readout Module is responsible for reading the RAW calorimeter data from synchronisation block.

This module creates RAW events, by reading fibre input data.
There are 40 ECAL and 9 HCAL fibre links.
The events are stored in Link Output FIFO ready to be sent to cFPGA via an MGT link.

Tidemark register are implemented for following FIFOs: TOB Readout: TOB FIFO, XTOB FIFO, L/O FIFO, BCN/LI_ID FIFO As the fill levels for TOBs, XTOBs and BCN/LI_ID FIFOs are identical, the Tidemark is implemented for XTOB e/g FIFO and shared for others 32-bit register now contains: bit(31:16) Tidemark fill value bit(15:0) Instantaneous fill value

RAW Readout: RAW input FIFO, L/O FIFO, BCN/LI_ID FIFO As the fill levels for for all 49 input data FIFOs are identical, the Tidemark is implemented for Link 0 only 32-bit register now contains: bit(31:16) Tidemark fill value bit(15:0) Instantaneous fill value

Tidemark registers are all cleared by Busy counter Reset pulse

Readout_ipb_slave Module is responsible for communication with IPBus. All registers in RAW and TOB blocks are accessed trough this module.

TOB Busy Counter is responsible for counting the Number of TOB Readout BUSY assertions. Cleared by Busy counter Reset pulse

RAW Busy Counter is responsible for counting the Number of RAW Readout BUSY assertions. Cleared by Busy counter Reset pulse

ECR Debug Counter is responsible for counting the Number ECR assertions. Cleared by ECR Debug Reset pulse

L1A Debug Counter is responsible for counting the Number EL1A assertions. Cleared by L1A Debug Reset pulse

TOB Busy Duration Counter is responsible for counting Duration that TOB Readout BUSY is asserted. Cleared by Busy counter Reset pulse

RAW Busy Duration Counter is responsible for counting Duration that RAW Readout BUSY is asserted. Cleared by Busy counter Reset pulse

Real Time Counter is responsible for counting the Number of 40MHz ticks. Cleared by Busy counter Reset pulse

TOB Double Word Counter is responsible for counting the Number identical double words transmitted to control FPGA.. Cleared by SPY RAM write address Reset pulse

L1A_cntr Module is responsible for generating L1A_ID. The first event has L1A_ID of ZERO. Cleared by L1A ID Reset pulse.

Author: Saeed Taghavi

Definition at line 213 of file Readout_logic_top.vhd.

The documentation for this class was generated from the following file:

Readout/src/Readout_logic_top.vhd

Processes

Signals

Attributes

Instantiations

Detailed Description