Top Level of Readout Logic for process FPGA. More...

Inheritance diagram for Readout_logic_top:

Entities
Behavioral	architecture
	Top Level of Readout Logic for process FPGA. More...

Libraries
IEEE
UNISIM
UNIMACRO
TOB_rdout_lib
ipbus_lib
algolib
infrastructure_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
vcomponents
data_type_pkg	Package <data_type_pkg>
TOB_rdout_ip_pkg	Package <TOB_rdout_ip_pkg>
ipbus
AlgoDataTypes	Package <AlgoDataTypes>

Generics
FPGA_NUMBER	integer := 1
	Integer used to distinguish different FPGAs having a slightly different firmware.

Ports
RST	in	std_logic
		Reset from 40MHz MMCM lock signal.
hw_addr	in	STD_LOGIC_VECTOR ( 1 downto 0 )
		FPGA Hardware Address.
ipb_rst	in	std_logic
		ipb_rst signal is input from master to slaves
ipb_clk	in	std_logic
		ipb_clk signal is input from master to slaves
IPb_in	in	ipb_wbus
		IPb_in signal going from master to slaves.
IPb_out	out	ipb_rbus
		IPb_out signal going from slaves to master.
clk_load_in	in	STD_LOGIC
		40Mhz input signal at 20% duty cycle
clk_40M_rdout	in	STD_LOGIC
		40Mhz input signal used only for RAW data readout
clk_200M_in	in	STD_LOGIC
		200Mhz input signal
clk_280M_in	in	STD_LOGIC
		280Mhz input signal
clk_40M_in	in	STD_LOGIC
		40Mhz input signal
shelf_number	in	STD_LOGIC_VECTOR ( 3 downto 0 )
		shelf number input
efex_slot_num	in	STD_LOGIC_VECTOR ( 3 downto 0 )
		eFEX slot number input
TOB_TXOUTCLK	in	STD_LOGIC
		TOB TXOUTCLK to read XTOB/TOB data to MGT for transmission to control FPGA.
RAW_TXOUTCLK	in	STD_LOGIC
		Calorimeter TXOUTCLK to read Calorimeter data to MGT for transmission to control FPGA.
XTOB_eg_in	in	AlgoXOutput
		XTOBs e/g 64b * 8.
XTOB_eg_Valid_flg_in	in	STD_LOGIC_VECTOR ( 7 downto 0 )
		8b XTOB e/g has valid d
XTOB_eg_sync_in	in	STD_LOGIC
		XTOB e/g sync sig.
XTOB_tau_in	in	AlgoXOutput
		XTOBs tau 64b.
XTOB_tau_Valid_flg_in	in	STD_LOGIC_VECTOR ( 7 downto 0 )
		8b XTOB tau has valid d
XTOB_tau_sync_in	in	STD_LOGIC
		XTOB tau sync sig.
OUT_XTOB_BCN	in	std_logic_vector ( 6 downto 0 )
		XTOB BC_ID with delay through ALGO/sorting block.
T_TOB_32b_in	in	STD_LOGIC_VECTOR ( 31 downto 0 )
		Sorted TOB data readout 32b * 7 in series, only 6 is used - F1 reads e/g TOBs and F2 reads tau TOBs.
T_TOB_sync_in	in	STD_LOGIC
		sorted TOB start signal
T_TOB_valid_in	in	STD_LOGIC
		sorted TOB valid signal
OUT_TOB_BCN	in	std_logic_vector ( 6 downto 0 )
		sorted TOB BC_ID with delay through ALGO/sorting block
L1A_in	in	STD_LOGIC
		L1A signal input.
ECR_in	in	STD_LOGIC
		ECR signal input.
BCR_in	in	STD_LOGIC
		BCR signal input.
TTC_read_all_in	in	STD_LOGIC
		Privilege Read signal input (previledge read)
local_BCN_out	out	STD_LOGIC_VECTOR ( 11 downto 0 )
		Local BCN generated in Process FPGA.
TTC_L1A_ID_EXT_in	in	STD_LOGIC_VECTOR ( 7 downto 0 )
		Extended L1A ID provided by TTC - ECRID.
TTC_L1A_ID_in	in	STD_LOGIC_VECTOR ( 23 downto 0 )
		L1A ID provided by TTC.
TTC_parity_in	in	STD_LOGIC
		Odd parity over ECR ID and L1A ID provided by TTC.
TOB_ready_in	in	std_logic
		Ready signal from control FPGA to receive TOBs data.
RAW_ready_in	in	std_logic
		Ready signal from control FPGA to receive RAW calorimeter data.
busy_raw	out	std_logic
		raw data busy out
busy_tob	out	std_logic
		tob data busy out
TOB_out_is_char	out	STD_LOGIC
		32b data out to MGT is CHAR
TOB_out	out	STD_LOGIC_VECTOR ( 31 downto 0 )
		32b sorted XTOB/TOB out to MGT
mgt_enable_in	in	STD_LOGIC_VECTOR ( 48 downto 0 )
RAW_data_in	in	RAW_data_227_type
		calorimeter data array 49 x 224b input frames
RAW_out_is_char	out	STD_LOGIC
		calorimeter data 32b out to MGT is CHAR
RAW_data_out	out	STD_LOGIC_VECTOR ( 31 downto 0 )
		calorimeter data 32b out to MGT

Detailed Description

Top Level of Readout Logic for process FPGA.

This is the top module of the Readout Logic The inputs are:

Calorimeter data extracted from the real-time path at the input to the algorithm block
XTOBs for tau or e/g data from the real-time path at the output of the algorithm block
Merged Sorted TOBs from the real-time path at the output of the merging block

The Readout output is two streams of 32b data and consists of:

RAW Calorimeter data
Merged Sorted TOBs & local XTOBs as defined in eFEX data format document.

Two streams of 32b data is fed to two MGTs through Link Output FIFOs for tranfer to Control FPGA

Readout Logic Block Diagram

This block consists of four submodules: Submodule 1 : TOBs_Readout Submodule 2 : RAW_data_Readout Submodule 3 : readout_ipb_slave Submodule 4 : L1A counter

TOBs_Readout Module is responsible for reading the merged sorted TOBs and local XTOBS from outputs of Algo Block, and creating a full events, storing only valid TOBs and XTOBs.

The events are stored in Link Output FIFO ready to be sent to Control FPGA via an MGT link.
Process FPGA 1 reads e/g TOBs and Process FPGA 2 reads tau TOBs, so same firmware in both FPGAs, use FPGA_NUMBER generic to differentiate.

RAW_data_Readout Module is responsible for reading the RAW calorimeter data from synchronisation block.

This module creates RAW events, by reading fibre input data.
There are 40 ECAL and 9 HCAL fibre links.
The events are stored in Link Output FIFO ready to be sent to cFPGA via an MGT link.

Tidemark register are implemented for following FIFOs: TOB Readout: TOB FIFO, XTOB FIFO, L/O FIFO, BCN/LI_ID FIFO As the fill levels for TOBs, XTOBs and BCN/LI_ID FIFOs are identical, the Tidemark is implemented for XTOB e/g FIFO and shared for others 32-bit register now contains: bit(31:16) Tidemark fill value bit(15:0) Instantaneous fill value

RAW Readout: RAW input FIFO, L/O FIFO, BCN/LI_ID FIFO As the fill levels for for all 49 input data FIFOs are identical, the Tidemark is implemented for Link 0 only 32-bit register now contains: bit(31:16) Tidemark fill value bit(15:0) Instantaneous fill value

Tidemark registers are all cleared by Busy counter Reset pulse

Readout_ipb_slave Module is responsible for communication with IPBus. All registers in RAW and TOB blocks are accessed trough this module.

TOB Busy Counter is responsible for counting the Number of TOB Readout BUSY assertions. Cleared by Busy counter Reset pulse

RAW Busy Counter is responsible for counting the Number of RAW Readout BUSY assertions. Cleared by Busy counter Reset pulse

ECR Debug Counter is responsible for counting the Number ECR assertions. Cleared by ECR Debug Reset pulse

L1A Debug Counter is responsible for counting the Number EL1A assertions. Cleared by L1A Debug Reset pulse

TOB Busy Duration Counter is responsible for counting Duration that TOB Readout BUSY is asserted. Cleared by Busy counter Reset pulse

RAW Busy Duration Counter is responsible for counting Duration that RAW Readout BUSY is asserted. Cleared by Busy counter Reset pulse

Real Time Counter is responsible for counting the Number of 40MHz ticks. Cleared by Busy counter Reset pulse

TOB Double Word Counter is responsible for counting the Number identical double words transmitted to control FPGA.. Cleared by SPY RAM write address Reset pulse

L1A_cntr Module is responsible for generating L1A_ID. The first event has L1A_ID of ZERO. Cleared by L1A ID Reset pulse.

Author: Saeed Taghavi

Definition at line 112 of file Readout_logic_top.vhd.

Member Data Documentation

◆ mgt_enable_in

mgt_enable_in in STD_LOGIC_VECTOR ( 48 downto 0 )

Port

RAW data readout signals MGT enable signals - use to enable/disable readout on error

Definition at line 202 of file Readout_logic_top.vhd.

The documentation for this class was generated from the following file:

Readout/src/Readout_logic_top.vhd

Entities

Libraries

Use Clauses

Generics

Ports

Detailed Description

Member Data Documentation

◆ mgt_enable_in