golden Package Reference

Package Body >> golden

Procedures
	P_RECORD_TO_PORTS( signal record_in: in efex_processor_input signal record_out: out efex_processor_output signal q_clk_gtrefclk_pad_n_in: out std_logic_vector ( 19 downto 0 ) signal q_clk_gtrefclk_pad_p_in: out std_logic_vector ( 19 downto 0 ) signal rxn_IN: out std_logic_vector ( 79 downto 0 ) signal rxp_IN: out std_logic_vector ( 79 downto 0 ) signal ttc_inform_p: out std_logic_vector ( 3 downto 0 ) signal ttc_inform_n: out std_logic_vector ( 3 downto 0 ) signal ttc_info: out std_logic_vector ( 37 downto 0 ) signal ttc_parity: out std_logic signal ctrl_TOB_ready_in: out std_logic signal ctrl_RAW_ready_in: out std_logic signal data_from_fpga_A_p: out std_logic_vector ( 32 downto 0 ) signal data_from_fpga_A_n: out std_logic_vector ( 32 downto 0 ) signal data_from_fpga_B_p: out std_logic_vector ( 32 downto 0 ) signal data_from_fpga_B_n: out std_logic_vector ( 32 downto 0 ) signal data_from_fpga_C_p: out std_logic_vector ( 32 downto 0 ) signal data_from_fpga_C_n: out std_logic_vector ( 32 downto 0 ) signal txn_OUT: in std_logic_vector ( 77 downto 0 ) signal txp_OUT: in std_logic_vector ( 77 downto 0 ) signal data_to_fpga_X_p: in std_logic_vector ( 32 downto 0 ) signal data_to_fpga_X_n: in std_logic_vector ( 32 downto 0 ) signal data_to_fpga_Y_p: in std_logic_vector ( 32 downto 0 ) signal data_to_fpga_Y_n: in std_logic_vector ( 32 downto 0 ) signal busy_raw: in std_logic signal busy_tob: in std_logic )
	mgts reference clocks
	P_CONTROL_RECORD_TO_PORTS( signal record_in: in efex_control_input signal record_out: out efex_control_output signal ttc_L1A_p: in std_logic_vector ( 3 downto 0 ) signal ttc_L1A_n: in std_logic_vector ( 3 downto 0 ) signal ttc_BCR_p: in std_logic_vector ( 3 downto 0 ) signal ttc_BCR_n: in std_logic_vector ( 3 downto 0 ) signal ttc_ECR_p: in std_logic_vector ( 3 downto 0 ) signal ttc_ECR_n: in std_logic_vector ( 3 downto 0 ) signal ttc_pr_rdout_p: in std_logic_vector ( 3 downto 0 ) signal ttc_pr_rdout_n: in std_logic_vector ( 3 downto 0 ) signal ttc_info_F1: in std_logic_vector ( 37 downto 0 ) signal ttc_info_F2: in std_logic_vector ( 37 downto 0 ) signal ttc_info_F3: in std_logic_vector ( 37 downto 0 ) signal ttc_info_F4: in std_logic_vector ( 37 downto 0 ) signal ttc_parity_F1: in std_logic signal ttc_parity_F2: in std_logic signal ttc_parity_F3: in std_logic signal ttc_parity_F4: in std_logic signal aurora_hub1_txp: in std_logic_vector ( 3 downto 0 ) signal aurora_hub1_txn: in std_logic_vector ( 3 downto 0 ) signal aurora_hub2_txp: in std_logic_vector ( 3 downto 0 ) signal aurora_hub2_txn: in std_logic_vector ( 3 downto 0 ) signal cntl_RAW_rdy_F1_out: in std_logic signal cntl_TOB_rdy_F1_out: in std_logic signal cntl_RAW_rdy_F2_out: in std_logic signal cntl_TOB_rdy_F2_out: in std_logic signal cntl_RAW_rdy_F3_out: in std_logic signal cntl_TOB_rdy_F3_out: in std_logic signal cntl_RAW_rdy_F4_out: in std_logic signal cntl_TOB_rdy_F4_out: in std_logic signal txp_OUT: in std_logic_vector ( 9 downto 0 ) signal txn_OUT: in std_logic_vector ( 9 downto 0 ) signal sk14: in std_logic signal sk15: in std_logic signal aurora_hub2_refclk1_p: out std_logic signal aurora_hub2_refclk1_n: out std_logic signal aurora_hub1_refclk1_p: out std_logic signal aurora_hub1_refclk1_n: out std_logic signal busy_raw: out std_logic_vector ( 3 downto 0 ) signal busy_tob: out std_logic_vector ( 3 downto 0 ) signal Q_CLK_GTREFCLK_PAD_N_IN: out std_logic_vector ( 2 downto 0 ) signal Q_CLK_GTREFCLK_PAD_P_IN: out std_logic_vector ( 2 downto 0 ) signal rxp_IN: out std_logic_vector ( 9 downto 0 ) signal rxn_IN: out std_logic_vector ( 9 downto 0 ) )
	tob data busy out
	P_RECORD_TO_PORTS( signal record_in: in efex_processor_input signal record_out: out efex_processor_output signal q_clk_gtrefclk_pad_n_in: out std_logic_vector ( 19 downto 0 ) signal q_clk_gtrefclk_pad_p_in: out std_logic_vector ( 19 downto 0 ) signal rxn_IN: out std_logic_vector ( 79 downto 0 ) signal rxp_IN: out std_logic_vector ( 79 downto 0 ) signal ttc_inform_p: out std_logic_vector ( 3 downto 0 ) signal ttc_inform_n: out std_logic_vector ( 3 downto 0 ) signal ttc_info: out std_logic_vector ( 37 downto 0 ) signal ttc_parity: out std_logic signal ctrl_TOB_ready_in: out std_logic signal ctrl_RAW_ready_in: out std_logic signal data_from_fpga_A_p: out std_logic_vector ( 32 downto 0 ) signal data_from_fpga_A_n: out std_logic_vector ( 32 downto 0 ) signal data_from_fpga_B_p: out std_logic_vector ( 32 downto 0 ) signal data_from_fpga_B_n: out std_logic_vector ( 32 downto 0 ) signal data_from_fpga_C_p: out std_logic_vector ( 32 downto 0 ) signal data_from_fpga_C_n: out std_logic_vector ( 32 downto 0 ) signal txn_OUT: in std_logic_vector ( 77 downto 0 ) signal txp_OUT: in std_logic_vector ( 77 downto 0 ) signal data_to_fpga_X_p: in std_logic_vector ( 32 downto 0 ) signal data_to_fpga_X_n: in std_logic_vector ( 32 downto 0 ) signal data_to_fpga_Y_p: in std_logic_vector ( 32 downto 0 ) signal data_to_fpga_Y_n: in std_logic_vector ( 32 downto 0 ) signal busy_raw: in std_logic signal busy_tob: in std_logic )
	mgts reference clocks
	P_CONTROL_RECORD_TO_PORTS( signal record_in: in efex_control_input signal record_out: out efex_control_output signal ttc_L1A_p: in std_logic_vector ( 3 downto 0 ) signal ttc_L1A_n: in std_logic_vector ( 3 downto 0 ) signal ttc_BCR_p: in std_logic_vector ( 3 downto 0 ) signal ttc_BCR_n: in std_logic_vector ( 3 downto 0 ) signal ttc_ECR_p: in std_logic_vector ( 3 downto 0 ) signal ttc_ECR_n: in std_logic_vector ( 3 downto 0 ) signal ttc_pr_rdout_p: in std_logic_vector ( 3 downto 0 ) signal ttc_pr_rdout_n: in std_logic_vector ( 3 downto 0 ) signal ttc_info_F1: in std_logic_vector ( 37 downto 0 ) signal ttc_info_F2: in std_logic_vector ( 37 downto 0 ) signal ttc_info_F3: in std_logic_vector ( 37 downto 0 ) signal ttc_info_F4: in std_logic_vector ( 37 downto 0 ) signal ttc_parity_F1: in std_logic signal ttc_parity_F2: in std_logic signal ttc_parity_F3: in std_logic signal ttc_parity_F4: in std_logic signal aurora_hub1_txp: in std_logic_vector ( 3 downto 0 ) signal aurora_hub1_txn: in std_logic_vector ( 3 downto 0 ) signal aurora_hub2_txp: in std_logic_vector ( 3 downto 0 ) signal aurora_hub2_txn: in std_logic_vector ( 3 downto 0 ) signal cntl_RAW_rdy_F1_out: in std_logic signal cntl_TOB_rdy_F1_out: in std_logic signal cntl_RAW_rdy_F2_out: in std_logic signal cntl_TOB_rdy_F2_out: in std_logic signal cntl_RAW_rdy_F3_out: in std_logic signal cntl_TOB_rdy_F3_out: in std_logic signal cntl_RAW_rdy_F4_out: in std_logic signal cntl_TOB_rdy_F4_out: in std_logic signal txp_OUT: in std_logic_vector ( 9 downto 0 ) signal txn_OUT: in std_logic_vector ( 9 downto 0 ) signal sk14: in std_logic signal sk15: in std_logic signal aurora_hub2_refclk1_p: out std_logic signal aurora_hub2_refclk1_n: out std_logic signal aurora_hub1_refclk1_p: out std_logic signal aurora_hub1_refclk1_n: out std_logic signal busy_raw: out std_logic_vector ( 3 downto 0 ) signal busy_tob: out std_logic_vector ( 3 downto 0 ) signal Q_CLK_GTREFCLK_PAD_N_IN: out std_logic_vector ( 2 downto 0 ) signal Q_CLK_GTREFCLK_PAD_P_IN: out std_logic_vector ( 2 downto 0 ) signal rxp_IN: out std_logic_vector ( 9 downto 0 ) signal rxn_IN: out std_logic_vector ( 9 downto 0 ) )
	tob data busy out

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
NUMERIC_STD

Records
efex_processor_input
efex_processor_output
efex_control_output
efex_control_input

Detailed Description

Definition at line 5 of file golden.vhd.

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The documentation for this class was generated from the following files:

• Infrastructure/process_Fpga_common/src/top/golden.vhd
• Infrastructure/process_Fpga_common/src/top/user.vhd