eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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user.vhd
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.all;
3 use IEEE.NUMERIC_STD.all;
4 
5 package golden is
6  type efex_processor_input is
7  record
8  q_clk_gtrefclk_pad_n_in : std_logic_vector (19 downto 0);
9  q_clk_gtrefclk_pad_p_in : std_logic_vector (19 downto 0);
10  rxn_IN : std_logic_vector (79 downto 0);
11  rxp_IN : std_logic_vector (79 downto 0);
12  data_from_fpga_A_p : std_logic_vector(32 downto 0);
13  data_from_fpga_A_n : std_logic_vector(32 downto 0);
14  data_from_fpga_B_p : std_logic_vector(32 downto 0);
15  data_from_fpga_B_n : std_logic_vector(32 downto 0);
16  data_from_fpga_C_p : std_logic_vector(32 downto 0);
17  data_from_fpga_C_n : std_logic_vector(32 downto 0);
18  ttc_inform_p : std_logic_vector(3 downto 0);
19  ttc_inform_n : std_logic_vector(3 downto 0);
20  ttc_info : std_logic_vector(37 downto 0);
21  ttc_parity : std_logic;
22  ctrl_TOB_ready_in : std_logic;
23  ctrl_RAW_ready_in : std_logic;
24 
25  end record;
26 
27  type efex_processor_output is
28  record
29  txn_OUT : std_logic_vector (77 downto 0);
30  txp_OUT : std_logic_vector (77 downto 0);
31  data_to_fpga_X_p : std_logic_vector(32 downto 0);
32  data_to_fpga_X_n : std_logic_vector(32 downto 0);
33  data_to_fpga_Y_p : std_logic_vector(32 downto 0);
34  data_to_fpga_Y_n : std_logic_vector(32 downto 0);
35  busy_raw : std_logic;
36  busy_tob : std_logic;
37 
38  end record;
39 
40  type efex_control_output is
41  record
42  ttc_L1A_p : std_logic_vector (3 downto 0);
43  ttc_L1A_n : std_logic_vector (3 downto 0);
44  ttc_BCR_p : std_logic_vector (3 downto 0);
45  ttc_BCR_n : std_logic_vector (3 downto 0);
46  ttc_ECR_p : std_logic_vector (3 downto 0);
47  ttc_ECR_n : std_logic_vector (3 downto 0);
48  ttc_pr_rdout_p : std_logic_vector (3 downto 0);
49  ttc_pr_rdout_n : std_logic_vector (3 downto 0);
50  ttc_info_F1 : std_logic_vector (37 downto 0);
51  ttc_info_F2 : std_logic_vector (37 downto 0);
52  ttc_info_F3 : std_logic_vector (37 downto 0);
53  ttc_info_F4 : std_logic_vector (37 downto 0);
54  ttc_parity_F1 : std_logic;
55  ttc_parity_F2 : std_logic;
56  ttc_parity_F3 : std_logic;
57  ttc_parity_F4 : std_logic;
58  aurora_hub1_txp : std_logic_vector (3 downto 0);
59  aurora_hub1_txn : std_logic_vector (3 downto 0);
60  aurora_hub2_txp : std_logic_vector (3 downto 0);
61  aurora_hub2_txn : std_logic_vector (3 downto 0);
62  cntl_RAW_rdy_F1_out : std_logic;
63  cntl_TOB_rdy_F1_out : std_logic;
64  cntl_RAW_rdy_F2_out : std_logic;
65  cntl_TOB_rdy_F2_out : std_logic;
66  cntl_RAW_rdy_F3_out : std_logic;
67  cntl_TOB_rdy_F3_out : std_logic;
68  cntl_RAW_rdy_F4_out : std_logic;
69  cntl_TOB_rdy_F4_out : std_logic;
70  txp_OUT : std_logic_vector(9 downto 0);
71  txn_OUT : std_logic_vector(9 downto 0);
72  sk14 : std_logic;
73  sk15 : std_logic;
74  end record;
75 
76  type efex_control_input is
77  record
78  aurora_hub2_refclk1_p : std_logic;
79  aurora_hub2_refclk1_n : std_logic;
80  aurora_hub1_refclk1_p : std_logic;
81  aurora_hub1_refclk1_n : std_logic;
82  busy_raw : std_logic_vector (3 downto 0);
83  busy_tob : std_logic_vector (3 downto 0);
84  Q_CLK_GTREFCLK_PAD_N_IN : std_logic_vector(2 downto 0);
85  Q_CLK_GTREFCLK_PAD_P_IN : std_logic_vector(2 downto 0);
86  rxp_IN : std_logic_vector (9 downto 0);
87  rxn_IN : std_logic_vector (9 downto 0);
88  end record;
89 
90  procedure P_RECORD_TO_PORTS (
91  signal record_in : in efex_processor_input;
92  signal record_out : out efex_processor_output;
93 
94  signal q_clk_gtrefclk_pad_n_in : out std_logic_vector (19 downto 0); --! mgts reference clocks
95  signal q_clk_gtrefclk_pad_p_in : out std_logic_vector (19 downto 0); --! mgts reference clocks
96  signal rxn_IN : out std_logic_vector (79 downto 0); --! mgt rx side inputs
97  signal rxp_IN : out std_logic_vector (79 downto 0); --! mgt rx side inputs
98  signal ttc_inform_p : out std_logic_vector(3 downto 0); --! ttc information that has L1A,BCR and ECR
99  signal ttc_inform_n : out std_logic_vector(3 downto 0); --! ttc information that has L1A,BCR and ECR
100  signal ttc_info : out std_logic_vector(37 downto 0); --! ttc info L1ID and ECRID (Phase-I) L0ID (Phase-II)
101  signal ttc_parity : out std_logic; --! Odd parity over ttc info
102  signal ctrl_TOB_ready_in : out std_logic; --! Ready signal from control FPGA to receive TOB data
103  signal ctrl_RAW_ready_in : out std_logic; --! Ready signal from control FPGA to receive RAW calorimeter data
104  signal data_from_fpga_A_p : out std_logic_vector(32 downto 0); --! merging data from another fpga
105  signal data_from_fpga_A_n : out std_logic_vector(32 downto 0); --! merging data from another fpga
106  signal data_from_fpga_B_p : out std_logic_vector(32 downto 0); --! merging data from another fpga
107  signal data_from_fpga_B_n : out std_logic_vector(32 downto 0); --! merging data from another fpga
108  signal data_from_fpga_C_p : out std_logic_vector(32 downto 0); --! merging data from another fpga
109  signal data_from_fpga_C_n : out std_logic_vector(32 downto 0); --! merging data from another fpga
110 
111  signal txn_OUT : in std_logic_vector (77 downto 0); --! mgts tx side outputs
112  signal txp_OUT : in std_logic_vector (77 downto 0); --! mgts tx side outputs
113  signal data_to_fpga_X_p : in std_logic_vector(32 downto 0); --! merging data from this fpga to another fpga
114  signal data_to_fpga_X_n : in std_logic_vector(32 downto 0); --! merging data from this fpga to another fpga
115  signal data_to_fpga_Y_p : in std_logic_vector(32 downto 0); --! merging data from this fpga to another fpga
116  signal data_to_fpga_Y_n : in std_logic_vector(32 downto 0); --! merging data from this fpga to another fpga --
117  signal busy_raw : in std_logic; --! raw data busy out
118  signal busy_tob : in std_logic --! tob data busy out
119  );
120 
121  procedure P_CONTROL_RECORD_TO_PORTS (
122  signal record_in : in efex_control_input;
123  signal record_out : out efex_control_output;
124 
125  signal ttc_L1A_p : in std_logic_vector (3 downto 0);
126  signal ttc_L1A_n : in std_logic_vector (3 downto 0);
127  signal ttc_BCR_p : in std_logic_vector (3 downto 0);
128  signal ttc_BCR_n : in std_logic_vector (3 downto 0);
129  signal ttc_ECR_p : in std_logic_vector (3 downto 0);
130  signal ttc_ECR_n : in std_logic_vector (3 downto 0);
131  signal ttc_pr_rdout_p : in std_logic_vector (3 downto 0);
132  signal ttc_pr_rdout_n : in std_logic_vector (3 downto 0);
133  signal ttc_info_F1 : in std_logic_vector (37 downto 0);
134  signal ttc_info_F2 : in std_logic_vector (37 downto 0);
135  signal ttc_info_F3 : in std_logic_vector (37 downto 0);
136  signal ttc_info_F4 : in std_logic_vector (37 downto 0);
137  signal ttc_parity_F1 : in std_logic;
138  signal ttc_parity_F2 : in std_logic;
139  signal ttc_parity_F3 : in std_logic;
140  signal ttc_parity_F4 : in std_logic;
141  signal aurora_hub1_txp : in std_logic_vector (3 downto 0);
142  signal aurora_hub1_txn : in std_logic_vector (3 downto 0);
143  signal aurora_hub2_txp : in std_logic_vector (3 downto 0);
144  signal aurora_hub2_txn : in std_logic_vector (3 downto 0);
145  signal cntl_RAW_rdy_F1_out : in std_logic;
146  signal cntl_TOB_rdy_F1_out : in std_logic;
147  signal cntl_RAW_rdy_F2_out : in std_logic;
148  signal cntl_TOB_rdy_F2_out : in std_logic;
149  signal cntl_RAW_rdy_F3_out : in std_logic;
150  signal cntl_TOB_rdy_F3_out : in std_logic;
151  signal cntl_RAW_rdy_F4_out : in std_logic;
152  signal cntl_TOB_rdy_F4_out : in std_logic;
153  signal txp_OUT : in std_logic_vector(9 downto 0);
154  signal txn_OUT : in std_logic_vector(9 downto 0);
155  signal sk14 : in std_logic;
156  signal sk15 : in std_logic;
157 
158  signal aurora_hub2_refclk1_p : out std_logic;
159  signal aurora_hub2_refclk1_n : out std_logic;
160  signal aurora_hub1_refclk1_p : out std_logic;
161  signal aurora_hub1_refclk1_n : out std_logic;
162  signal busy_raw : out std_logic_vector (3 downto 0);
163  signal busy_tob : out std_logic_vector (3 downto 0);
164  signal Q_CLK_GTREFCLK_PAD_N_IN : out std_logic_vector(2 downto 0);
165  signal Q_CLK_GTREFCLK_PAD_P_IN : out std_logic_vector(2 downto 0);
166  signal rxp_IN : out std_logic_vector (9 downto 0);
167  signal rxn_IN : out std_logic_vector (9 downto 0));
168 end package golden;
169 
170 package body golden is
171  procedure P_RECORD_TO_PORTS (
172  signal record_in : in efex_processor_input;
173  signal record_out : out efex_processor_output;
174 
175  signal q_clk_gtrefclk_pad_n_in : out std_logic_vector (19 downto 0);
176  signal q_clk_gtrefclk_pad_p_in : out std_logic_vector (19 downto 0);
177  signal rxn_IN : out std_logic_vector (79 downto 0);
178  signal rxp_IN : out std_logic_vector (79 downto 0);
179  signal ttc_inform_p : out std_logic_vector(3 downto 0);
180  signal ttc_inform_n : out std_logic_vector(3 downto 0);
181  signal ttc_info : out std_logic_vector(37 downto 0);
182  signal ttc_parity : out std_logic;
183  signal ctrl_TOB_ready_in : out std_logic;
184  signal ctrl_RAW_ready_in : out std_logic;
185  signal data_from_fpga_A_p : out std_logic_vector(32 downto 0);
186  signal data_from_fpga_A_n : out std_logic_vector(32 downto 0);
187  signal data_from_fpga_B_p : out std_logic_vector(32 downto 0);
188  signal data_from_fpga_B_n : out std_logic_vector(32 downto 0);
189  signal data_from_fpga_C_p : out std_logic_vector(32 downto 0);
190  signal data_from_fpga_C_n : out std_logic_vector(32 downto 0);
191  signal txn_OUT : in std_logic_vector (77 downto 0);
192  signal txp_OUT : in std_logic_vector (77 downto 0);
193  signal data_to_fpga_X_p : in std_logic_vector(32 downto 0);
194  signal data_to_fpga_X_n : in std_logic_vector(32 downto 0);
195  signal data_to_fpga_Y_p : in std_logic_vector(32 downto 0);
196  signal data_to_fpga_Y_n : in std_logic_vector(32 downto 0);
197  signal busy_raw : in std_logic;
198  signal busy_tob : in std_logic
199  ) is
200  begin -- procedure P_RECORD_TO_PORTS
201 
202  q_clk_gtrefclk_pad_n_in <= record_in.q_clk_gtrefclk_pad_n_in;
203  q_clk_gtrefclk_pad_p_in <= record_in.q_clk_gtrefclk_pad_p_in;
204  rxn_IN <= record_in.rxn_IN;
205  rxp_IN <= record_in.rxp_IN;
206  ttc_inform_p <= record_in.ttc_inform_p;
207  ttc_inform_n <= record_in.ttc_inform_n;
208  ttc_info <= record_in.ttc_info;
209  ttc_parity <= record_in.ttc_parity;
210  ctrl_TOB_ready_in <= record_in.ctrl_TOB_ready_in;
211  ctrl_RAW_ready_in <= record_in.ctrl_RAW_ready_in;
212  data_from_fpga_A_p <= record_in.data_from_fpga_A_p;
213  data_from_fpga_A_n <= record_in.data_from_fpga_A_n;
214  data_from_fpga_B_p <= record_in.data_from_fpga_B_p;
215  data_from_fpga_B_n <= record_in.data_from_fpga_B_n;
216  data_from_fpga_C_p <= record_in.data_from_fpga_C_p;
217  data_from_fpga_C_n <= record_in.data_from_fpga_C_n;
218 
219  record_out.txn_OUT <= txn_OUT;
220  record_out.txp_OUT <= txp_OUT;
221  record_out.data_to_fpga_X_p <= data_to_fpga_X_p;
222  record_out.data_to_fpga_X_n <= data_to_fpga_X_n;
223  record_out.data_to_fpga_Y_p <= data_to_fpga_Y_p;
224  record_out.data_to_fpga_Y_n <= data_to_fpga_Y_n;
225  record_out.busy_raw <= busy_raw;
226  record_out.busy_tob <= busy_tob;
227  end procedure P_RECORD_TO_PORTS;
228 
229  procedure P_CONTROL_RECORD_TO_PORTS (
230  signal record_in : in efex_control_input;
231  signal record_out : out efex_control_output;
232 
233  signal ttc_L1A_p : in std_logic_vector (3 downto 0);
234  signal ttc_L1A_n : in std_logic_vector (3 downto 0);
235  signal ttc_BCR_p : in std_logic_vector (3 downto 0);
236  signal ttc_BCR_n : in std_logic_vector (3 downto 0);
237  signal ttc_ECR_p : in std_logic_vector (3 downto 0);
238  signal ttc_ECR_n : in std_logic_vector (3 downto 0);
239  signal ttc_pr_rdout_p : in std_logic_vector (3 downto 0);
240  signal ttc_pr_rdout_n : in std_logic_vector (3 downto 0);
241  signal ttc_info_F1 : in std_logic_vector (37 downto 0);
242  signal ttc_info_F2 : in std_logic_vector (37 downto 0);
243  signal ttc_info_F3 : in std_logic_vector (37 downto 0);
244  signal ttc_info_F4 : in std_logic_vector (37 downto 0);
245  signal ttc_parity_F1 : in std_logic;
246  signal ttc_parity_F2 : in std_logic;
247  signal ttc_parity_F3 : in std_logic;
248  signal ttc_parity_F4 : in std_logic;
249  signal aurora_hub1_txp : in std_logic_vector (3 downto 0);
250  signal aurora_hub1_txn : in std_logic_vector (3 downto 0);
251  signal aurora_hub2_txp : in std_logic_vector (3 downto 0);
252  signal aurora_hub2_txn : in std_logic_vector (3 downto 0);
253  signal cntl_RAW_rdy_F1_out : in std_logic;
254  signal cntl_TOB_rdy_F1_out : in std_logic;
255  signal cntl_RAW_rdy_F2_out : in std_logic;
256  signal cntl_TOB_rdy_F2_out : in std_logic;
257  signal cntl_RAW_rdy_F3_out : in std_logic;
258  signal cntl_TOB_rdy_F3_out : in std_logic;
259  signal cntl_RAW_rdy_F4_out : in std_logic;
260  signal cntl_TOB_rdy_F4_out : in std_logic;
261  signal txp_OUT : in std_logic_vector(9 downto 0);
262  signal txn_OUT : in std_logic_vector(9 downto 0);
263  signal sk14 : in std_logic;
264  signal sk15 : in std_logic;
265 
266  signal aurora_hub2_refclk1_p : out std_logic;
267  signal aurora_hub2_refclk1_n : out std_logic;
268  signal aurora_hub1_refclk1_p : out std_logic;
269  signal aurora_hub1_refclk1_n : out std_logic;
270  signal busy_raw : out std_logic_vector (3 downto 0);
271  signal busy_tob : out std_logic_vector (3 downto 0);
272  signal Q_CLK_GTREFCLK_PAD_N_IN : out std_logic_vector(2 downto 0);
273  signal Q_CLK_GTREFCLK_PAD_P_IN : out std_logic_vector(2 downto 0);
274  signal rxp_IN : out std_logic_vector (9 downto 0);
275  signal rxn_IN : out std_logic_vector (9 downto 0)) is
276 
277  begin
278  record_out.ttc_L1A_p <= ttc_L1A_p;
279  record_out.ttc_L1A_n <= ttc_L1A_n;
280  record_out.ttc_BCR_p <= ttc_BCR_p;
281  record_out.ttc_BCR_n <= ttc_BCR_n;
282  record_out.ttc_ECR_p <= ttc_ECR_p;
283  record_out.ttc_ECR_n <= ttc_ECR_n;
284  record_out.ttc_pr_rdout_p <= ttc_pr_rdout_p;
285  record_out.ttc_pr_rdout_n <= ttc_pr_rdout_n;
286  record_out.ttc_info_F1 <= ttc_info_F1;
287  record_out.ttc_info_F2 <= ttc_info_F2;
288  record_out.ttc_info_F3 <= ttc_info_F3;
289  record_out.ttc_info_F4 <= ttc_info_F4;
290  record_out.ttc_parity_F1 <= ttc_parity_F1;
291  record_out.ttc_parity_F2 <= ttc_parity_F2;
292  record_out.ttc_parity_F3 <= ttc_parity_F3;
293  record_out.ttc_parity_F4 <= ttc_parity_F4;
294  record_out.aurora_hub1_txp <= aurora_hub1_txp;
295  record_out.aurora_hub1_txn <= aurora_hub1_txn;
296  record_out.aurora_hub2_txp <= aurora_hub2_txp;
297  record_out.aurora_hub2_txn <= aurora_hub2_txn;
298  record_out.cntl_RAW_rdy_F1_out <= cntl_RAW_rdy_F1_out;
299  record_out.cntl_TOB_rdy_F1_out <= cntl_TOB_rdy_F1_out;
300  record_out.cntl_RAW_rdy_F2_out <= cntl_RAW_rdy_F2_out;
301  record_out.cntl_TOB_rdy_F2_out <= cntl_TOB_rdy_F2_out;
302  record_out.cntl_RAW_rdy_F3_out <= cntl_RAW_rdy_F3_out;
303  record_out.cntl_TOB_rdy_F3_out <= cntl_TOB_rdy_F3_out;
304  record_out.cntl_RAW_rdy_F4_out <= cntl_RAW_rdy_F4_out;
305  record_out.cntl_TOB_rdy_F4_out <= cntl_TOB_rdy_F4_out;
306  record_out.txp_OUT <= txp_OUT;
307  record_out.txn_OUT <= txn_OUT;
308  record_out.sk14 <= sk14;
309  record_out.sk15 <= sk15;
310 
311  aurora_hub2_refclk1_p <= record_in.aurora_hub2_refclk1_p;
312  aurora_hub2_refclk1_n <= record_in.aurora_hub2_refclk1_n;
313  aurora_hub1_refclk1_p <= record_in.aurora_hub1_refclk1_p;
314  aurora_hub1_refclk1_n <= record_in.aurora_hub1_refclk1_n;
315  busy_raw <= record_in.busy_raw;
316  busy_tob <= record_in.busy_tob;
317  Q_CLK_GTREFCLK_PAD_N_IN <= record_in.Q_CLK_GTREFCLK_PAD_N_IN;
318  Q_CLK_GTREFCLK_PAD_P_IN <= record_in.Q_CLK_GTREFCLK_PAD_P_IN;
319  rxp_IN <= record_in.rxp_IN;
320  rxn_IN <= record_in.rxn_IN;
321 
322  end procedure P_CONTROL_RECORD_TO_PORTS;
323 
324 end golden;
golden
Definition: golden.vhd:5
golden.P_RECORD_TO_PORTS
P_RECORD_TO_PORTSrecord_in,record_out,q_clk_gtrefclk_pad_n_in,q_clk_gtrefclk_pad_p_in,rxn_IN,rxp_IN,ttc_inform_p,ttc_inform_n,ttc_info,ttc_parity,ctrl_TOB_ready_in,ctrl_RAW_ready_in,data_from_fpga_A_p,data_from_fpga_A_n,data_from_fpga_B_p,data_from_fpga_B_n,data_from_fpga_C_p,data_from_fpga_C_n,txn_OUT,txp_OUT,data_to_fpga_X_p,data_to_fpga_X_n,data_to_fpga_Y_p,data_to_fpga_Y_n,busy_raw,busy_tob,
mgts reference clocks
Definition: golden.vhd:28
golden.P_CONTROL_RECORD_TO_PORTS
P_CONTROL_RECORD_TO_PORTSrecord_in,record_out,ttc_L1A_p,ttc_L1A_n,ttc_BCR_p,ttc_BCR_n,ttc_ECR_p,ttc_ECR_n,ttc_pr_rdout_p,ttc_pr_rdout_n,ttc_info_F1,ttc_info_F2,ttc_info_F3,ttc_info_F4,ttc_parity_F1,ttc_parity_F2,ttc_parity_F3,ttc_parity_F4,aurora_hub1_txp,aurora_hub1_txn,aurora_hub2_txp,aurora_hub2_txn,cntl_RAW_rdy_F1_out,cntl_TOB_rdy_F1_out,cntl_RAW_rdy_F2_out,cntl_TOB_rdy_F2_out,cntl_RAW_rdy_F3_out,cntl_TOB_rdy_F3_out,cntl_RAW_rdy_F4_out,cntl_TOB_rdy_F4_out,txp_OUT,txn_OUT,sk14,sk15,aurora_hub2_refclk1_p,aurora_hub2_refclk1_n,aurora_hub1_refclk1_p,aurora_hub1_refclk1_n,busy_raw,busy_tob,Q_CLK_GTREFCLK_PAD_N_IN,Q_CLK_GTREFCLK_PAD_P_IN,rxp_IN,rxn_IN,
tob data busy out
Definition: golden.vhd:60
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