eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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golden.vhd
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.all;
3 use IEEE.NUMERIC_STD.all;
4 
5 package golden is
6  type efex_processor_input is
7  record
8  dummy : std_logic;
9 
10  end record;
11 
12  type efex_processor_output is
13  record
14  dummy : std_logic;
15  end record;
16 
17  type efex_control_output is
18  record
19  dummy : std_logic;
20  end record;
21 
22  type efex_control_input is
23  record
24  dummy : std_logic;
25  end record;
26 
27 
28  procedure P_RECORD_TO_PORTS (
29  signal record_in : in efex_processor_input;
30  signal record_out : out efex_processor_output;
31 
32  signal q_clk_gtrefclk_pad_n_in : out std_logic_vector (19 downto 0); --! mgts reference clocks
33  signal q_clk_gtrefclk_pad_p_in : out std_logic_vector (19 downto 0); --! mgts reference clocks
34  signal rxn_IN : out std_logic_vector (79 downto 0); --! mgt rx side inputs
35  signal rxp_IN : out std_logic_vector (79 downto 0); --! mgt rx side inputs
36  signal ttc_inform_p : out std_logic_vector(3 downto 0); --! ttc information that has L1A,BCR and ECR
37  signal ttc_inform_n : out std_logic_vector(3 downto 0); --! ttc information that has L1A,BCR and ECR
38  signal ttc_info : out std_logic_vector(37 downto 0); --! ttc information L1ID and ECRID (Phase-I) L0ID (Phase-II)
39  signal ttc_parity : out std_logic; --! Odd parity over ttc ttc_info
40  signal ctrl_TOB_ready_in : out std_logic; --! Ready signal from control FPGA to receive TOB data
41  signal ctrl_RAW_ready_in : out std_logic; --! Ready signal from control FPGA to receive RAW calorimeter data
42  signal data_from_fpga_A_p : out std_logic_vector(32 downto 0); --! merging data from another fpga
43  signal data_from_fpga_A_n : out std_logic_vector(32 downto 0); --! merging data from another fpga
44  signal data_from_fpga_B_p : out std_logic_vector(32 downto 0); --! merging data from another fpga
45  signal data_from_fpga_B_n : out std_logic_vector(32 downto 0); --! merging data from another fpga
46  signal data_from_fpga_C_p : out std_logic_vector(32 downto 0); --! merging data from another fpga
47  signal data_from_fpga_C_n : out std_logic_vector(32 downto 0); --! merging data from another fpga
48 
49  signal txn_OUT : in std_logic_vector (77 downto 0); --! mgts tx side outputs
50  signal txp_OUT : in std_logic_vector (77 downto 0); --! mgts tx side outputs
51  signal data_to_fpga_X_p : in std_logic_vector(32 downto 0); --! merging data from this fpga to another fpga
52  signal data_to_fpga_X_n : in std_logic_vector(32 downto 0); --! merging data from this fpga to another fpga
53  signal data_to_fpga_Y_p : in std_logic_vector(32 downto 0); --! merging data from this fpga to another fpga
54  signal data_to_fpga_Y_n : in std_logic_vector(32 downto 0); --! merging data from this fpga to another fpga --
55  signal busy_raw : in std_logic; --! raw data busy out
56  signal busy_tob : in std_logic --! tob data busy out
57  );
58 
59 
60  procedure P_CONTROL_RECORD_TO_PORTS (
61  signal record_in : in efex_control_input;
62  signal record_out : out efex_control_output;
63 
64  signal ttc_L1A_p : in std_logic_vector (3 downto 0);
65  signal ttc_L1A_n : in std_logic_vector (3 downto 0);
66  signal ttc_BCR_p : in std_logic_vector (3 downto 0);
67  signal ttc_BCR_n : in std_logic_vector (3 downto 0);
68  signal ttc_ECR_p : in std_logic_vector (3 downto 0);
69  signal ttc_ECR_n : in std_logic_vector (3 downto 0);
70  signal ttc_pr_rdout_p : in std_logic_vector (3 downto 0);
71  signal ttc_pr_rdout_n : in std_logic_vector (3 downto 0);
72  signal ttc_info_F1 : in std_logic_vector (37 downto 0);
73  signal ttc_info_F2 : in std_logic_vector (37 downto 0);
74  signal ttc_info_F3 : in std_logic_vector (37 downto 0);
75  signal ttc_info_F4 : in std_logic_vector (37 downto 0);
76  signal ttc_parity_F1 : in std_logic;
77  signal ttc_parity_F2 : in std_logic;
78  signal ttc_parity_F3 : in std_logic;
79  signal ttc_parity_F4 : in std_logic;
80  signal aurora_hub1_txp : in std_logic_vector (3 downto 0);
81  signal aurora_hub1_txn : in std_logic_vector (3 downto 0);
82  signal aurora_hub2_txp : in std_logic_vector (3 downto 0);
83  signal aurora_hub2_txn : in std_logic_vector (3 downto 0);
84  signal cntl_RAW_rdy_F1_out : in std_logic;
85  signal cntl_TOB_rdy_F1_out : in std_logic;
86  signal cntl_RAW_rdy_F2_out : in std_logic;
87  signal cntl_TOB_rdy_F2_out : in std_logic;
88  signal cntl_RAW_rdy_F3_out : in std_logic;
89  signal cntl_TOB_rdy_F3_out : in std_logic;
90  signal cntl_RAW_rdy_F4_out : in std_logic;
91  signal cntl_TOB_rdy_F4_out : in std_logic;
92  signal txp_OUT : in std_logic_vector(9 downto 0);
93  signal txn_OUT : in std_logic_vector(9 downto 0);
94  signal sk14 : in std_logic;
95  signal sk15 : in std_logic;
96 
97  signal aurora_hub2_refclk1_p : out std_logic;
98  signal aurora_hub2_refclk1_n : out std_logic;
99  signal aurora_hub1_refclk1_p : out std_logic;
100  signal aurora_hub1_refclk1_n : out std_logic;
101  signal busy_raw : out std_logic_vector (3 downto 0);
102  signal busy_tob : out std_logic_vector (3 downto 0);
103  signal Q_CLK_GTREFCLK_PAD_N_IN : out std_logic_vector(2 downto 0);
104  signal Q_CLK_GTREFCLK_PAD_P_IN : out std_logic_vector(2 downto 0);
105  signal rxp_IN : out std_logic_vector (9 downto 0);
106  signal rxn_IN : out std_logic_vector (9 downto 0));
107 end package golden;
108 
109 package body golden is
110  procedure P_RECORD_TO_PORTS (
111  signal record_in : in efex_processor_input;
112  signal record_out : out efex_processor_output;
113 
114  signal q_clk_gtrefclk_pad_n_in : out std_logic_vector (19 downto 0);
115  signal q_clk_gtrefclk_pad_p_in : out std_logic_vector (19 downto 0);
116  signal rxn_IN : out std_logic_vector (79 downto 0);
117  signal rxp_IN : out std_logic_vector (79 downto 0);
118  signal ttc_inform_p : out std_logic_vector(3 downto 0);
119  signal ttc_inform_n : out std_logic_vector(3 downto 0);
120  signal ttc_info : out std_logic_vector(37 downto 0);
121  signal ttc_parity : out std_logic;
122  signal ctrl_TOB_ready_in : out std_logic;
123  signal ctrl_RAW_ready_in : out std_logic;
124  signal data_from_fpga_A_p : out std_logic_vector(32 downto 0);
125  signal data_from_fpga_A_n : out std_logic_vector(32 downto 0);
126  signal data_from_fpga_B_p : out std_logic_vector(32 downto 0);
127  signal data_from_fpga_B_n : out std_logic_vector(32 downto 0);
128  signal data_from_fpga_C_p : out std_logic_vector(32 downto 0);
129  signal data_from_fpga_C_n : out std_logic_vector(32 downto 0);
130  signal txn_OUT : in std_logic_vector (77 downto 0);
131  signal txp_OUT : in std_logic_vector (77 downto 0);
132  signal data_to_fpga_X_p : in std_logic_vector(32 downto 0);
133  signal data_to_fpga_X_n : in std_logic_vector(32 downto 0);
134  signal data_to_fpga_Y_p : in std_logic_vector(32 downto 0);
135  signal data_to_fpga_Y_n : in std_logic_vector(32 downto 0);
136  signal busy_raw : in std_logic;
137  signal busy_tob : in std_logic
138  ) is
139  begin -- procedure P_RECORD_TO_PORTS
140 
141  q_clk_gtrefclk_pad_n_in <= (others => '0');
142  q_clk_gtrefclk_pad_p_in <= (others => '0');
143  rxn_IN <= (others => '0');
144  rxp_IN <= (others => '0');
145  ttc_inform_p <= (others => '0');
146  ttc_inform_n <= (others => '0');
147  ttc_info <= (others => '0');
148  ttc_parity <= '1';
149  ctrl_TOB_ready_in <= '0';
150  ctrl_RAW_ready_in <= '0';
151  data_from_fpga_A_p <= (others => '0');
152  data_from_fpga_A_n <= (others => '0');
153  data_from_fpga_B_p <= (others => '0');
154  data_from_fpga_B_n <= (others => '0');
155  data_from_fpga_C_p <= (others => '0');
156  data_from_fpga_C_n <= (others => '0');
157 
158  record_out.dummy <= '0';
159  end procedure P_RECORD_TO_PORTS;
160 
161  procedure P_CONTROL_RECORD_TO_PORTS (
162  signal record_in : in efex_control_input;
163  signal record_out : out efex_control_output;
164 
165  signal ttc_L1A_p : in std_logic_vector (3 downto 0);
166  signal ttc_L1A_n : in std_logic_vector (3 downto 0);
167  signal ttc_BCR_p : in std_logic_vector (3 downto 0);
168  signal ttc_BCR_n : in std_logic_vector (3 downto 0);
169  signal ttc_ECR_p : in std_logic_vector (3 downto 0);
170  signal ttc_ECR_n : in std_logic_vector (3 downto 0);
171  signal ttc_pr_rdout_p : in std_logic_vector (3 downto 0);
172  signal ttc_pr_rdout_n : in std_logic_vector (3 downto 0);
173  signal ttc_info_F1 : in std_logic_vector (37 downto 0);
174  signal ttc_info_F2 : in std_logic_vector (37 downto 0);
175  signal ttc_info_F3 : in std_logic_vector (37 downto 0);
176  signal ttc_info_F4 : in std_logic_vector (37 downto 0);
177  signal ttc_parity_F1 : in std_logic;
178  signal ttc_parity_F2 : in std_logic;
179  signal ttc_parity_F3 : in std_logic;
180  signal ttc_parity_F4 : in std_logic;
181  signal aurora_hub1_txp : in std_logic_vector (3 downto 0);
182  signal aurora_hub1_txn : in std_logic_vector (3 downto 0);
183  signal aurora_hub2_txp : in std_logic_vector (3 downto 0);
184  signal aurora_hub2_txn : in std_logic_vector (3 downto 0);
185  signal cntl_RAW_rdy_F1_out : in std_logic;
186  signal cntl_TOB_rdy_F1_out : in std_logic;
187  signal cntl_RAW_rdy_F2_out : in std_logic;
188  signal cntl_TOB_rdy_F2_out : in std_logic;
189  signal cntl_RAW_rdy_F3_out : in std_logic;
190  signal cntl_TOB_rdy_F3_out : in std_logic;
191  signal cntl_RAW_rdy_F4_out : in std_logic;
192  signal cntl_TOB_rdy_F4_out : in std_logic;
193  signal txp_OUT : in std_logic_vector(9 downto 0);
194  signal txn_OUT : in std_logic_vector(9 downto 0);
195  signal sk14 : in std_logic;
196  signal sk15 : in std_logic;
197 
198  signal aurora_hub2_refclk1_p : out std_logic;
199  signal aurora_hub2_refclk1_n : out std_logic;
200  signal aurora_hub1_refclk1_p : out std_logic;
201  signal aurora_hub1_refclk1_n : out std_logic;
202  signal busy_raw : out std_logic_vector (3 downto 0);
203  signal busy_tob : out std_logic_vector (3 downto 0);
204  signal Q_CLK_GTREFCLK_PAD_N_IN : out std_logic_vector(2 downto 0);
205  signal Q_CLK_GTREFCLK_PAD_P_IN : out std_logic_vector(2 downto 0);
206  signal rxp_IN : out std_logic_vector (9 downto 0);
207  signal rxn_IN : out std_logic_vector (9 downto 0)) is
208 
209  begin
210  aurora_hub2_refclk1_p <= '0';
211  aurora_hub2_refclk1_n <= '0';
212  aurora_hub1_refclk1_p <= '0';
213  aurora_hub1_refclk1_n <= '0';
214  busy_raw <= (others => '0');
215  busy_tob <= (others => '0');
216  Q_CLK_GTREFCLK_PAD_N_IN <= (others => '0');
217  Q_CLK_GTREFCLK_PAD_P_IN <= (others => '0');
218  rxp_IN <= (others => '0');
219  rxn_IN <= (others => '0');
220 
221  end procedure P_CONTROL_RECORD_TO_PORTS;
222 
223 end golden;
golden
Definition: golden.vhd:5
golden.P_RECORD_TO_PORTS
P_RECORD_TO_PORTSrecord_in,record_out,q_clk_gtrefclk_pad_n_in,q_clk_gtrefclk_pad_p_in,rxn_IN,rxp_IN,ttc_inform_p,ttc_inform_n,ttc_info,ttc_parity,ctrl_TOB_ready_in,ctrl_RAW_ready_in,data_from_fpga_A_p,data_from_fpga_A_n,data_from_fpga_B_p,data_from_fpga_B_n,data_from_fpga_C_p,data_from_fpga_C_n,txn_OUT,txp_OUT,data_to_fpga_X_p,data_to_fpga_X_n,data_to_fpga_Y_p,data_to_fpga_Y_n,busy_raw,busy_tob,
mgts reference clocks
Definition: golden.vhd:28
golden.P_CONTROL_RECORD_TO_PORTS
P_CONTROL_RECORD_TO_PORTSrecord_in,record_out,ttc_L1A_p,ttc_L1A_n,ttc_BCR_p,ttc_BCR_n,ttc_ECR_p,ttc_ECR_n,ttc_pr_rdout_p,ttc_pr_rdout_n,ttc_info_F1,ttc_info_F2,ttc_info_F3,ttc_info_F4,ttc_parity_F1,ttc_parity_F2,ttc_parity_F3,ttc_parity_F4,aurora_hub1_txp,aurora_hub1_txn,aurora_hub2_txp,aurora_hub2_txn,cntl_RAW_rdy_F1_out,cntl_TOB_rdy_F1_out,cntl_RAW_rdy_F2_out,cntl_TOB_rdy_F2_out,cntl_RAW_rdy_F3_out,cntl_TOB_rdy_F3_out,cntl_RAW_rdy_F4_out,cntl_TOB_rdy_F4_out,txp_OUT,txn_OUT,sk14,sk15,aurora_hub2_refclk1_p,aurora_hub2_refclk1_n,aurora_hub1_refclk1_p,aurora_hub1_refclk1_n,busy_raw,busy_tob,Q_CLK_GTREFCLK_PAD_N_IN,Q_CLK_GTREFCLK_PAD_P_IN,rxp_IN,rxn_IN,
tob data busy out
Definition: golden.vhd:60
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