MGT_4_quad_gen Entity Reference

MGT quad generation. More...

Inheritance diagram for MGT_4_quad_gen:

Entities
Behavioral	architecture
	MGT quad generation. More...

Libraries
IEEE
work

Use Clauses
STD_LOGIC_1164
mgt_type	Package <mgt_type>

Generics
num_quad_tx_rx	natural := 20
QUAD_ENABLE	std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' )

Ports
clk280	in	std_logic
TTC_CLK	in	std_logic
MGT_CLK_GTREFCLK_PAD_N_IN	in	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
MGT_CLK_GTREFCLK_PAD_P_IN	in	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
mgt_TXUSRCLK_OUT	out	std_logic_vector ( 4 * num_quad_tx_rx- 1 downto 0 )
mgt_RXUSRCLK_OUT	out	std_logic_vector ( 4 * num_quad_tx_rx- 1 downto 0 )
mgt_SOFT_RESET_TX_IN	in	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
mgt_SOFT_RESET_RX_IN	in	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
RXN_IN	in	mgt_rx_array ( num_quad_tx_rx- 1 downto 0 )
RXP_IN	in	mgt_rx_array ( num_quad_tx_rx- 1 downto 0 )
TXN_IN	out	mgt_tx_array ( num_quad_tx_rx- 1 downto 0 )
TXP_IN	out	mgt_tx_array ( num_quad_tx_rx- 1 downto 0 )
rxdata_quad_array	out	mgt_rxdata_array ( num_quad_tx_rx- 1 downto 0 )
txdata_quad_array	in	mgt_txdata_array ( num_quad_tx_rx- 1 downto 0 )
mgt_DATA_VALID_IN	in	std_logic_vector ( 4 * num_quad_tx_rx- 1 downto 0 )
mgt_TX_FSM_RESET_DONE	out	std_logic_vector ( 4 * num_quad_tx_rx- 1 downto 0 )
mgt_RX_FSM_RESET_DONE	out	std_logic_vector ( 4 * num_quad_tx_rx- 1 downto 0 )
rxbyteisaligned_quad_array	out	mgt_rxbyteisaligned_array ( num_quad_tx_rx- 1 downto 0 )
rxresetdone_quad_array	out	mgt_rxresetdone_array ( num_quad_tx_rx- 1 downto 0 )
txresetdone_quad_array	out	mgt_txresetdone_array ( num_quad_tx_rx- 1 downto 0 )
gt_rxpd_array	in	mgt_rxpd_array ( num_quad_tx_rx- 1 downto 0 )
gt_txpd_array	in	mgt_txpd_array ( num_quad_tx_rx- 1 downto 0 )
loopback_quad_array	in	mgt_loopback_array ( num_quad_tx_rx- 1 downto 0 )
rxchariscomma_quad_array	out	mgt_rxchariskcomm_array ( num_quad_tx_rx- 1 downto 0 )
rxcharisk_quad_array	out	mgt_rxcharisk_array ( num_quad_tx_rx- 1 downto 0 )
txcharisk_quad_array	in	mgt_txcharisk_array ( num_quad_tx_rx- 1 downto 0 )
txbufstatus_quad_array	out	mgt_txbufstatus_array ( num_quad_tx_rx- 1 downto 0 )
rxbyterealign_quad_array	out	mgt_rxbyterealign_array ( num_quad_tx_rx- 1 downto 0 )
rxcommadet_quad_array	out	mgt_rxcommadet_array ( num_quad_tx_rx- 1 downto 0 )
rxdisperr_quad_array	out	mgt_rxdisperr_array ( num_quad_tx_rx- 1 downto 0 )
rxnotintable_quad_array	out	mgt_rxnotintable_array ( num_quad_tx_rx- 1 downto 0 )
mgt_QPLLREFCLKLOST_OUT	out	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
mgt_QPLLLOCK_OUT	out	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )

Detailed Description

MGT quad generation.

MGT_4_quad_gen generates num_quad_tx_rx MGT quads that contain both transmitters and receivers. This is done via an intermediate 'wrapper' level of hierarchy that ties off unused signals and thus simplifies the interface to the MGTs at this level. The transceiver and receiver in each MGT operate independently of each other: they do not comprise a duplex link. They are grouped together in the VHDL only because they are co-located in the same MGT.

On the receive path, this component performs the following functions:

• Receives 16 × 11.2 Gb/s serial data streams (from the LAr and/or Tile calorimeters, but this block is agnostic with respect to the source)
• Decodes the data using the 8b/10b line code;
• Recovers a 280 MHz clock from the data;
• Converts each serial data stream to parallel data, 32 bits wide, synchronous with the recovered 280 MHz clock;
• Performs word-alignment of the output data to the 280 MHz clock (such that bit 0 of each 32-bit word is located in the correct place)
• Outputs, for each of the 16 32-bit data outputs, a signal indicating when a comma has been received (the signal COMMADET from the Xilinx MGT block).

Definition at line 43 of file MGT_4_quad_gen.vhd.

Member Data Documentation

IEEE

IEEE

Library

On the transmit path, this component performs the following functions:

• Receives seven 32-bit words at 280 MHz (comprising TOB data and trailer words, but this component is agnostic with respect to the data/trailer content);
• Fans out the data four ways, to comprise eight 32-bit words at 280 MHz;
• Encodes each 32-bit word using 8b/10b encoding, to form eight 40-bit words at 280 MHz;
• Converts each stream of 40-bit 280 MHz data into a serial stream at 11.2 Gb/s and outputs this (to L1Topo).

The MGTs here are implemented using Xilinx IP. MGT settings:

• Transceiver: GTH
  • Line rate (Tx and Rx): 11.2 Gb/s
  • Reference clock (Tx and Rx): 280 MHz
  • External data width: 32 bits
  • Encoding/decoding scheme: 8b/10b
  • Comma value = K28.5

Definition at line 35 of file MGT_4_quad_gen.vhd.

STD_LOGIC_1164

STD_LOGIC_1164

use clause

Author

Mohammed Syiad

Francesco Gonnella

Definition at line 36 of file MGT_4_quad_gen.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/MGT/vhdl/MGT_4_quad_gen.vhd