eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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MGT_4_quad_gen.vhd
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1 
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34 
35 library IEEE;
36 use IEEE.STD_LOGIC_1164.all;
37 --library mgt_lib;
38 --use mgt_lib.mgt_type.all;
39 library work;
40 use work.mgt_type.all;
41 
43 entity MGT_4_quad_gen is
44  generic(num_quad_tx_rx : natural := 20;
45  QUAD_ENABLE : std_logic_vector (19 downto 0) := (others => '0')
46  );
47  port (
48  clk280 : in std_logic;
49  TTC_CLK : in std_logic;
50  MGT_CLK_GTREFCLK_PAD_N_IN : in std_logic_vector(num_quad_tx_rx-1 downto 0);
51  MGT_CLK_GTREFCLK_PAD_P_IN : in std_logic_vector(num_quad_tx_rx-1 downto 0);
52 
53  mgt_TXUSRCLK_OUT : out std_logic_vector(4*num_quad_tx_rx -1 downto 0);
54  mgt_RXUSRCLK_OUT : out std_logic_vector(4*num_quad_tx_rx -1 downto 0);
55 
56  mgt_SOFT_RESET_TX_IN : in std_logic_vector(num_quad_tx_rx -1 downto 0);
57  mgt_SOFT_RESET_RX_IN : in std_logic_vector(num_quad_tx_rx -1 downto 0);
58  -- data
59  RXN_IN : in mgt_rx_array(num_quad_tx_rx-1 downto 0);
60  RXP_IN : in mgt_rx_array(num_quad_tx_rx-1 downto 0);
61  TXN_IN : out mgt_tx_array(num_quad_tx_rx-1 downto 0);
62  TXP_IN : out mgt_tx_array(num_quad_tx_rx-1 downto 0);
63 
64  rxdata_quad_array : out mgt_rxdata_array (num_quad_tx_rx -1 downto 0);
65  txdata_quad_array : in mgt_txdata_array (num_quad_tx_rx -1 downto 0);
66  -- status and monitoring
67  mgt_DATA_VALID_IN : in std_logic_vector(4*num_quad_tx_rx -1 downto 0);
68  mgt_TX_FSM_RESET_DONE : out std_logic_vector(4*num_quad_tx_rx -1 downto 0);
69  mgt_RX_FSM_RESET_DONE : out std_logic_vector(4*num_quad_tx_rx -1 downto 0);
70  rxbyteisaligned_quad_array : out mgt_rxbyteisaligned_array(num_quad_tx_rx -1 downto 0);
71  rxresetdone_quad_array : out mgt_rxresetdone_array (num_quad_tx_rx -1 downto 0);
72  txresetdone_quad_array : out mgt_txresetdone_array (num_quad_tx_rx -1 downto 0);
73 
74  gt_rxpd_array : in mgt_rxpd_array (num_quad_tx_rx -1 downto 0);
75  gt_txpd_array : in mgt_txpd_array (num_quad_tx_rx -1 downto 0);
76  loopback_quad_array : in mgt_loopback_array (num_quad_tx_rx-1 downto 0);
77  rxchariscomma_quad_array : out mgt_rxchariskcomm_array (num_quad_tx_rx -1 downto 0);
78  rxcharisk_quad_array : out mgt_rxcharisk_array (num_quad_tx_rx -1 downto 0);
79  txcharisk_quad_array : in mgt_txcharisk_array (num_quad_tx_rx -1 downto 0);
80  txbufstatus_quad_array : out mgt_txbufstatus_array (num_quad_tx_rx -1 downto 0);
81  rxbyterealign_quad_array : out mgt_rxbyterealign_array (num_quad_tx_rx -1 downto 0);
82  rxcommadet_quad_array : out mgt_rxcommadet_array (num_quad_tx_rx -1 downto 0);
83  rxdisperr_quad_array : out mgt_rxdisperr_array (num_quad_tx_rx -1 downto 0);
84  rxnotintable_quad_array : out mgt_rxnotintable_array (num_quad_tx_rx -1 downto 0);
85  mgt_QPLLREFCLKLOST_OUT : out std_logic_vector(num_quad_tx_rx-1 downto 0);
86  mgt_QPLLLOCK_OUT : out std_logic_vector (num_quad_tx_rx -1 downto 0)
87  );
88 end MGT_4_quad_gen;
89 
91 architecture Behavioral of MGT_4_quad_gen is
92 
93 --- mgt signal declarations
94 
95  signal RXN_IN_tx_rx, RXP_IN_tx_rx : mgt_rx_array (num_quad_tx_rx-1 downto 0);
96  signal TXN_IN_tx_rx, TXP_IN_tx_rx : mgt_tx_array (num_quad_tx_rx-1 downto 0);
97 
98 begin
99 
100  MGT_GEN : for i in 0 to num_quad_tx_rx-1
101  generate
102 
103  mgt_1quad_Rx_Tx : entity work.mgt_selection_wrapper
104  -- This part will generate 4 quads, 4*4 = 16 mgts.
105  generic map (ENABLED => QUAD_ENABLE(i))
106  port map (
107  clk280 => clk280,
108  SOFT_RESET_TX_IN => mgt_SOFT_RESET_TX_IN(i),
109  SOFT_RESET_RX_IN => mgt_SOFT_RESET_RX_IN(i),
110  RXN_IN => RXN_IN(i).RXN_IN,
111  RXP_IN => RXP_IN(i).RXP_IN,
112  TXN_OUT => TXN_IN(i).TXN_OUT,
113  TXP_OUT => TXP_IN(i).TXP_OUT,
114  Q0_CLK0_GTREFCLK_PAD_N_IN => MGT_CLK_GTREFCLK_PAD_N_IN(i),
115  Q0_CLK0_GTREFCLK_PAD_P_IN => MGT_CLK_GTREFCLK_PAD_P_IN(i),
116 
117  GT0_TX_FSM_RESET_DONE_OUT => mgt_TX_FSM_RESET_DONE(4*i),
118  GT0_RX_FSM_RESET_DONE_OUT => mgt_RX_FSM_RESET_DONE(4*i),
119  GT0_DATA_VALID_IN => mgt_DATA_VALID_IN (4*i),
120 
121  GT1_TX_FSM_RESET_DONE_OUT => mgt_TX_FSM_RESET_DONE(4*i+1),
122  GT1_RX_FSM_RESET_DONE_OUT => mgt_RX_FSM_RESET_DONE(4*i+1),
123  GT1_DATA_VALID_IN => mgt_DATA_VALID_IN (4*i+1),
124 
125  GT2_TX_FSM_RESET_DONE_OUT => mgt_TX_FSM_RESET_DONE(4*i+2),
126  GT2_RX_FSM_RESET_DONE_OUT => mgt_RX_FSM_RESET_DONE(4*i+2),
127  GT2_DATA_VALID_IN => mgt_DATA_VALID_IN (4*i+2),
128 
129  GT3_TX_FSM_RESET_DONE_OUT => mgt_TX_FSM_RESET_DONE(4*i+3),
130  GT3_RX_FSM_RESET_DONE_OUT => mgt_RX_FSM_RESET_DONE(4*i+3),
131  GT3_DATA_VALID_IN => mgt_DATA_VALID_IN (4*i+3),
132 
133  GT0_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(4*i),
134  GT0_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(4*i),
135  GT1_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(4*i+1),
136  GT1_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(4*i+1),
137  GT2_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(4*i+2),
138  GT2_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(4*i+2),
139  GT3_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(4*i+3),
140  GT3_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(4*i+3),
141 
142  --_________________________________________________________________________
143  --GT0 (X0Y0)
144  --____________________________CHANNEL PORTS________________________________
145 
146  gt0_loopback_in => loopback_quad_array(i).gt0_loopback_in,
147  gt0_rxpd_in => gt_rxpd_array(i).gt0_rxpd,
148  gt0_txpd_in => gt_txpd_array(i).gt0_txpd,
149  gt0_rxdata_out => rxdata_quad_array (i).gt0_rxdata_out,
150  gt0_rxdisperr_out => rxdisperr_quad_array(i).gt0_rxdisperr,
151  gt0_rxnotintable_out => rxnotintable_quad_array(i).gt0_rxnotintable,
152  gt0_rxbyterealign_out => rxbyterealign_quad_array(i).gt0_rxbyterealign,
153  gt0_rxcommadet_out => rxcommadet_quad_array(i).gt0_rxcommadet,
154  gt0_rxbyteisaligned_out => rxbyteisaligned_quad_array(i).gt0_rxbyteisaligned,
155  gt0_rxchariscomma_out => rxchariscomma_quad_array(i).gt0_rxchariscomma_out,
156  gt0_rxcharisk_out => rxcharisk_quad_array(i).gt0_rxcharisk_out,
157  gt0_rxresetdone_out => rxresetdone_quad_array(i).gt0_rxresetdone,
158  gt0_txdata_in => txdata_quad_array(i).gt0_txdata_in,
159  gt0_txresetdone_out => txresetdone_quad_array(i).gt0_txresetdone,
160  gt0_txcharisk_in => txcharisk_quad_array (i).gt0_txcharisk,
161  gt0_txbufstatus_out => txbufstatus_quad_array(i).gt0_txbufstatus,
162 
163  --GT1 (X0Y1)
164  --____________________________CHANNEL PORTS________________________________
165  gt1_loopback_in => loopback_quad_array(i).gt0_loopback_in,
166  gt1_rxpd_in => gt_rxpd_array(i).gt1_rxpd,
167  gt1_txpd_in => gt_txpd_array(i).gt1_txpd,
168  gt1_rxdata_out => rxdata_quad_array (i).gt1_rxdata_out,
169  gt1_rxdisperr_out => rxdisperr_quad_array(i).gt1_rxdisperr,
170  gt1_rxnotintable_out => rxnotintable_quad_array(i).gt1_rxnotintable,
171  gt1_rxbyterealign_out => rxbyterealign_quad_array(i).gt1_rxbyterealign,
172  gt1_rxcommadet_out => rxcommadet_quad_array(i).gt1_rxcommadet,
173  gt1_rxbyteisaligned_out => rxbyteisaligned_quad_array(i).gt1_rxbyteisaligned,
174  gt1_rxchariscomma_out => rxchariscomma_quad_array(i).gt1_rxchariscomma_out,
175  gt1_rxcharisk_out => rxcharisk_quad_array(i).gt1_rxcharisk_out,
176  gt1_rxresetdone_out => rxresetdone_quad_array(i).gt1_rxresetdone,
177  gt1_txdata_in => txdata_quad_array(i).gt1_txdata_in,
178  gt1_txresetdone_out => txresetdone_quad_array(i).gt1_txresetdone,
179  gt1_txcharisk_in => txcharisk_quad_array (i).gt1_txcharisk,
180  gt1_txbufstatus_out => txbufstatus_quad_array(i).gt1_txbufstatus,
181  --GT2 (X0Y2)
182  --____________________________CHANNEL PORTS________________________________
183  gt2_loopback_in => loopback_quad_array(i).gt0_loopback_in,
184  gt2_rxpd_in => gt_rxpd_array(i).gt2_rxpd,
185  gt2_txpd_in => gt_txpd_array(i).gt2_txpd,
186  gt2_rxdata_out => rxdata_quad_array (i).gt2_rxdata_out,
187  gt2_rxdisperr_out => rxdisperr_quad_array(i).gt2_rxdisperr,
188  gt2_rxnotintable_out => rxnotintable_quad_array(i).gt2_rxnotintable,
189  gt2_rxbyterealign_out => rxbyterealign_quad_array(i).gt2_rxbyterealign,
190  gt2_rxcommadet_out => rxcommadet_quad_array(i).gt2_rxcommadet,
191  gt2_rxbyteisaligned_out => rxbyteisaligned_quad_array(i).gt2_rxbyteisaligned,
192  gt2_rxchariscomma_out => rxchariscomma_quad_array(i).gt2_rxchariscomma_out,
193  gt2_rxcharisk_out => rxcharisk_quad_array(i).gt2_rxcharisk_out,
194  gt2_rxresetdone_out => rxresetdone_quad_array(i).gt2_rxresetdone,
195  gt2_txdata_in => txdata_quad_array(i).gt2_txdata_in,
196  gt2_txresetdone_out => txresetdone_quad_array(i).gt2_txresetdone,
197  gt2_txcharisk_in => txcharisk_quad_array (i).gt2_txcharisk,
198  gt2_txbufstatus_out => txbufstatus_quad_array(i).gt2_txbufstatus,
199 
200  --GT3 (X0Y3)
201  --____________________________CHANNEL PORTS________________________________
202  gt3_loopback_in => loopback_quad_array(i).gt0_loopback_in,
203  gt3_rxpd_in => gt_rxpd_array(i).gt3_rxpd,
204  gt3_txpd_in => gt_txpd_array(i).gt3_txpd,
205  gt3_rxdata_out => rxdata_quad_array (i).gt3_rxdata_out,
206  gt3_rxdisperr_out => rxdisperr_quad_array(i).gt3_rxdisperr,
207  gt3_rxnotintable_out => rxnotintable_quad_array(i).gt3_rxnotintable,
208  gt3_rxbyterealign_out => rxbyterealign_quad_array(i).gt3_rxbyterealign,
209  gt3_rxcommadet_out => rxcommadet_quad_array(i).gt3_rxcommadet,
210  gt3_rxbyteisaligned_out => rxbyteisaligned_quad_array(i).gt3_rxbyteisaligned,
211  gt3_rxchariscomma_out => rxchariscomma_quad_array(i).gt3_rxchariscomma_out,
212  gt3_rxcharisk_out => rxcharisk_quad_array(i).gt3_rxcharisk_out,
213  gt3_rxresetdone_out => rxresetdone_quad_array(i).gt3_rxresetdone,
214  gt3_txdata_in => txdata_quad_array(i).gt3_txdata_in,
215  gt3_txresetdone_out => txresetdone_quad_array(i).gt3_txresetdone,
216  gt3_txcharisk_in => txcharisk_quad_array (i).gt3_txcharisk,
217  gt3_txbufstatus_out => txbufstatus_quad_array(i).gt3_txbufstatus,
218 
219  --____________________________COMMON PORTS________________________________
220  GT0_QPLLLOCK_OUT => mgt_QPLLLOCK_OUT(i), --.GT0_QPLLLOCK_OUT,
221  GT0_QPLLREFCLKLOST_OUT => mgt_QPLLREFCLKLOST_OUT(i), --.GT0_QPLLREFCLKLOST_OUT,
222  sysclk_in => TTC_CLK
223  );
224  end generate MGT_GEN;
225 end Behavioral;
MGT_4_quad_gen.Behavioral
MGT quad generation.
Definition: MGT_4_quad_gen.vhd:91
MGT_4_quad_gen
MGT quad generation.
Definition: MGT_4_quad_gen.vhd:43
mgt_selection_wrapper
mgt selection wrapper
Definition: mgt_selection_wrapper.vhd:15
mgt_selection_wrapper.gt1_rxdata_out
out gt1_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt1.
Definition: mgt_selection_wrapper.vhd:121
mgt_selection_wrapper.gt3_txbufstatus_out
out gt3_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt3.
Definition: mgt_selection_wrapper.vhd:201
mgt_selection_wrapper.gt3_rxbyteisaligned_out
out gt3_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt3.
Definition: mgt_selection_wrapper.vhd:186
mgt_selection_wrapper.gt2_txresetdone_out
out gt2_txresetdone_out std_logic
Transmit Ports - TX Fabric Clock Output Control Ports for gt2.
Definition: mgt_selection_wrapper.vhd:167
mgt_selection_wrapper.GT3_DATA_VALID_IN
in GT3_DATA_VALID_IN std_logic
status of data valid in not used gt3
Definition: mgt_selection_wrapper.vhd:63
mgt_selection_wrapper.gt1_txdata_in
in gt1_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface gt1.
Definition: mgt_selection_wrapper.vhd:135
mgt_selection_wrapper.GT0_TXUSRCLK_OUT
out GT0_TXUSRCLK_OUT std_logic
tx user clock out gt0
Definition: mgt_selection_wrapper.vhd:65
mgt_selection_wrapper.gt0_txbufstatus_out
out gt0_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt0.
Definition: mgt_selection_wrapper.vhd:110
mgt_selection_wrapper.TXN_OUT
out TXN_OUT std_logic_vector( 3 downto 0)
tx quad output
Definition: mgt_selection_wrapper.vhd:35
mgt_selection_wrapper.gt0_rxdisperr_out
out gt0_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt0.
Definition: mgt_selection_wrapper.vhd:92
mgt_selection_wrapper.GT3_TX_FSM_RESET_DONE_OUT
out GT3_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt3
Definition: mgt_selection_wrapper.vhd:59
mgt_selection_wrapper.GT2_RX_FSM_RESET_DONE_OUT
out GT2_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt2
Definition: mgt_selection_wrapper.vhd:55
mgt_selection_wrapper.GT0_DATA_VALID_IN
in GT0_DATA_VALID_IN std_logic
status of data valid in not used gt0
Definition: mgt_selection_wrapper.vhd:45
mgt_selection_wrapper.GT0_QPLLLOCK_OUT
out GT0_QPLLLOCK_OUT std_logic
COMMON PORTS.
Definition: mgt_selection_wrapper.vhd:204
mgt_selection_wrapper.gt2_rxresetdone_out
out gt2_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt2.
Definition: mgt_selection_wrapper.vhd:163
mgt_selection_wrapper.gt2_rxpd_in
in gt2_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt2.
Definition: mgt_selection_wrapper.vhd:148
mgt_selection_wrapper.gt1_txbufstatus_out
out gt1_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt1.
Definition: mgt_selection_wrapper.vhd:141
mgt_selection_wrapper.gt0_rxdata_out
out gt0_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt0.
Definition: mgt_selection_wrapper.vhd:90
mgt_selection_wrapper.GT2_TXUSRCLK_OUT
out GT2_TXUSRCLK_OUT std_logic
tx user clock out gt2
Definition: mgt_selection_wrapper.vhd:73
mgt_selection_wrapper.gt3_rxdisperr_out
out gt3_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt3.
Definition: mgt_selection_wrapper.vhd:183
mgt_selection_wrapper.gt2_loopback_in
in gt2_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt2.
Definition: mgt_selection_wrapper.vhd:146
mgt_selection_wrapper.gt1_rxresetdone_out
out gt1_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt1.
Definition: mgt_selection_wrapper.vhd:133
mgt_selection_wrapper.gt0_txdata_in
in gt0_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface gt0.
Definition: mgt_selection_wrapper.vhd:104
mgt_selection_wrapper.gt3_rxdata_out
out gt3_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt3.
Definition: mgt_selection_wrapper.vhd:181
mgt_selection_wrapper.gt2_rxbyteisaligned_out
out gt2_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt2.
Definition: mgt_selection_wrapper.vhd:156
mgt_selection_wrapper.gt3_loopback_in
in gt3_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt3.
Definition: mgt_selection_wrapper.vhd:176
mgt_selection_wrapper.GT1_RX_FSM_RESET_DONE_OUT
out GT1_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt1
Definition: mgt_selection_wrapper.vhd:49
mgt_selection_wrapper.gt0_rxchariscomma_out
out gt0_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt0.
Definition: mgt_selection_wrapper.vhd:99
mgt_selection_wrapper.gt0_txresetdone_out
out gt0_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt0.
Definition: mgt_selection_wrapper.vhd:106
mgt_selection_wrapper.GT3_TXUSRCLK_OUT
out GT3_TXUSRCLK_OUT std_logic
tx user clock out gt3
Definition: mgt_selection_wrapper.vhd:77
mgt_selection_wrapper.GT3_RX_FSM_RESET_DONE_OUT
out GT3_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt3
Definition: mgt_selection_wrapper.vhd:61
mgt_selection_wrapper.gt2_rxdisperr_out
out gt2_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt2.
Definition: mgt_selection_wrapper.vhd:153
mgt_selection_wrapper.GT1_DATA_VALID_IN
in GT1_DATA_VALID_IN std_logic
status of data valid in not used gt1
Definition: mgt_selection_wrapper.vhd:51
mgt_selection_wrapper.gt0_rxresetdone_out
out gt0_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt0.
Definition: mgt_selection_wrapper.vhd:102
mgt_selection_wrapper.gt3_txdata_in
in gt3_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt3.
Definition: mgt_selection_wrapper.vhd:195
mgt_selection_wrapper.gt3_rxresetdone_out
out gt3_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt3.
Definition: mgt_selection_wrapper.vhd:193
mgt_selection_wrapper.gt2_txbufstatus_out
out gt2_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt2.
Definition: mgt_selection_wrapper.vhd:171
mgt_selection_wrapper.gt3_txcharisk_in
in gt3_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt3.
Definition: mgt_selection_wrapper.vhd:199
mgt_selection_wrapper.clk280
in clk280 std_logic
fabric clock of 280MHz
Definition: mgt_selection_wrapper.vhd:26
mgt_selection_wrapper.gt0_rxpd_in
in gt0_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt0.
Definition: mgt_selection_wrapper.vhd:87
mgt_selection_wrapper.gt2_rxchariscomma_out
out gt2_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt2.
Definition: mgt_selection_wrapper.vhd:160
mgt_selection_wrapper.GT3_RXUSRCLK_OUT
out GT3_RXUSRCLK_OUT std_logic
rx user clock out gt3
Definition: mgt_selection_wrapper.vhd:79
mgt_selection_wrapper.gt0_rxbyteisaligned_out
out gt0_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt0.
Definition: mgt_selection_wrapper.vhd:95
mgt_selection_wrapper.GT0_TX_FSM_RESET_DONE_OUT
out GT0_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt0
Definition: mgt_selection_wrapper.vhd:41
mgt_selection_wrapper.SOFT_RESET_TX_IN
in SOFT_RESET_TX_IN std_logic
soft reset of tx quad
Definition: mgt_selection_wrapper.vhd:28
mgt_selection_wrapper.GT1_RXUSRCLK_OUT
out GT1_RXUSRCLK_OUT std_logic
rx user clock out gt1
Definition: mgt_selection_wrapper.vhd:71
mgt_selection_wrapper.gt1_txresetdone_out
out gt1_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt1.
Definition: mgt_selection_wrapper.vhd:137
mgt_selection_wrapper.gt1_txcharisk_in
in gt1_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt1.
Definition: mgt_selection_wrapper.vhd:139
mgt_selection_wrapper.gt1_rxpd_in
in gt1_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt1.
Definition: mgt_selection_wrapper.vhd:118
mgt_selection_wrapper.gt1_rxbyteisaligned_out
out gt1_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt1.
Definition: mgt_selection_wrapper.vhd:126
mgt_selection_wrapper.RXN_IN
in RXN_IN std_logic_vector( 3 downto 0)
rx quad input
Definition: mgt_selection_wrapper.vhd:32
mgt_selection_wrapper.GT2_RXUSRCLK_OUT
out GT2_RXUSRCLK_OUT std_logic
rx user clock out gt2
Definition: mgt_selection_wrapper.vhd:75
mgt_selection_wrapper.gt1_rxchariscomma_out
out gt1_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt1.
Definition: mgt_selection_wrapper.vhd:130
mgt_selection_wrapper.gt2_rxdata_out
out gt2_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt2.
Definition: mgt_selection_wrapper.vhd:151
mgt_selection_wrapper.gt3_rxpd_in
in gt3_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt3.
Definition: mgt_selection_wrapper.vhd:178
mgt_selection_wrapper.Q0_CLK0_GTREFCLK_PAD_N_IN
in Q0_CLK0_GTREFCLK_PAD_N_IN std_logic
clock input to the quad
Definition: mgt_selection_wrapper.vhd:38
mgt_selection_wrapper.gt2_txcharisk_in
in gt2_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt2.
Definition: mgt_selection_wrapper.vhd:169
mgt_selection_wrapper.gt3_rxchariscomma_out
out gt3_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt3.
Definition: mgt_selection_wrapper.vhd:190
mgt_selection_wrapper.gt2_txdata_in
in gt2_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt2.
Definition: mgt_selection_wrapper.vhd:165
mgt_selection_wrapper.GT2_TX_FSM_RESET_DONE_OUT
out GT2_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt2
Definition: mgt_selection_wrapper.vhd:53
mgt_selection_wrapper.gt1_loopback_in
in gt1_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt1.
Definition: mgt_selection_wrapper.vhd:116
mgt_selection_wrapper.gt0_txcharisk_in
in gt0_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports gt0.
Definition: mgt_selection_wrapper.vhd:108
mgt_selection_wrapper.GT0_RXUSRCLK_OUT
out GT0_RXUSRCLK_OUT std_logic
rx user clock out gt0
Definition: mgt_selection_wrapper.vhd:67
mgt_selection_wrapper.GT0_RX_FSM_RESET_DONE_OUT
out GT0_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gto
Definition: mgt_selection_wrapper.vhd:43
mgt_selection_wrapper.GT2_DATA_VALID_IN
in GT2_DATA_VALID_IN std_logic
status of data valid in not used gt2
Definition: mgt_selection_wrapper.vhd:57
mgt_selection_wrapper.gt1_rxdisperr_out
out gt1_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt1.
Definition: mgt_selection_wrapper.vhd:123
mgt_selection_wrapper.gt3_txresetdone_out
out gt3_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt3.
Definition: mgt_selection_wrapper.vhd:197
mgt_selection_wrapper.SOFT_RESET_RX_IN
in SOFT_RESET_RX_IN std_logic
soft reset of rx quad
Definition: mgt_selection_wrapper.vhd:30
mgt_selection_wrapper.gt0_loopback_in
in gt0_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt0.
Definition: mgt_selection_wrapper.vhd:85
mgt_selection_wrapper.GT1_TX_FSM_RESET_DONE_OUT
out GT1_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt1
Definition: mgt_selection_wrapper.vhd:47
mgt_selection_wrapper.GT1_TXUSRCLK_OUT
out GT1_TXUSRCLK_OUT std_logic
tx user clock out gt1
Definition: mgt_selection_wrapper.vhd:69
mgt_type
Definition: mgt_type_pkg.vhd:4
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