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ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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mgt_selection_wrapper.vhd
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1 
6 
7 library ieee;
8 use ieee.std_logic_1164.all;
9 use ieee.numeric_std.all;
10 use ieee.std_logic_unsigned.all;
11 library UNISIM;
12 use UNISIM.VCOMPONENTS.all;
13 
15 entity mgt_selection_wrapper is
16  generic
17  (
18  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
19  STABLE_CLOCK_PERIOD : integer := 16;
20  ENABLED : std_logic := '1'
21  );
22 
23  port
24  (
26  clk280 : in std_logic;
28  SOFT_RESET_TX_IN : in std_logic;
30  SOFT_RESET_RX_IN : in std_logic;
32  RXN_IN : in std_logic_vector(3 downto 0);
33  RXP_IN : in std_logic_vector(3 downto 0);
35  TXN_OUT : out std_logic_vector(3 downto 0);
36  TXP_OUT : out std_logic_vector(3 downto 0);
38  Q0_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
39  Q0_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
41  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
43  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
45  GT0_DATA_VALID_IN : in std_logic;
47  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
49  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
51  GT1_DATA_VALID_IN : in std_logic;
53  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
55  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
57  GT2_DATA_VALID_IN : in std_logic;
59  GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
61  GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
63  GT3_DATA_VALID_IN : in std_logic;
65  GT0_TXUSRCLK_OUT : out std_logic;
67  GT0_RXUSRCLK_OUT : out std_logic;
69  GT1_TXUSRCLK_OUT : out std_logic;
71  GT1_RXUSRCLK_OUT : out std_logic;
73  GT2_TXUSRCLK_OUT : out std_logic;
75  GT2_RXUSRCLK_OUT : out std_logic;
77  GT3_TXUSRCLK_OUT : out std_logic;
79  GT3_RXUSRCLK_OUT : out std_logic;
80 
81  --_________________________________________________________________________
82  --GT0 (X0Y0)
83  --____________________________CHANNEL PORTS________________________________
85  gt0_loopback_in : in std_logic_vector(2 downto 0);
87  gt0_rxpd_in : in std_logic_vector(1 downto 0);
88  gt0_txpd_in : in std_logic_vector(1 downto 0);
90  gt0_rxdata_out : out std_logic_vector(31 downto 0);
92  gt0_rxdisperr_out : out std_logic_vector(3 downto 0);
93  gt0_rxnotintable_out : out std_logic_vector(3 downto 0);
95  gt0_rxbyteisaligned_out : out std_logic;
96  gt0_rxbyterealign_out : out std_logic;
97  gt0_rxcommadet_out : out std_logic;
99  gt0_rxchariscomma_out : out std_logic_vector(3 downto 0);
100  gt0_rxcharisk_out : out std_logic_vector(3 downto 0);
102  gt0_rxresetdone_out : out std_logic;
104  gt0_txdata_in : in std_logic_vector(31 downto 0);
106  gt0_txresetdone_out : out std_logic;
108  gt0_txcharisk_in : in std_logic_vector(3 downto 0);
110  gt0_txbufstatus_out : out std_logic_vector(1 downto 0);
111 
112  -- _______________________________________________________________________
113  --GT1 (X0Y1)
114  --____________________________CHANNEL PORTS________________________________
116  gt1_loopback_in : in std_logic_vector(2 downto 0);
118  gt1_rxpd_in : in std_logic_vector(1 downto 0);
119  gt1_txpd_in : in std_logic_vector(1 downto 0);
121  gt1_rxdata_out : out std_logic_vector(31 downto 0);
123  gt1_rxdisperr_out : out std_logic_vector(3 downto 0);
124  gt1_rxnotintable_out : out std_logic_vector(3 downto 0);
126  gt1_rxbyteisaligned_out : out std_logic;
127  gt1_rxbyterealign_out : out std_logic;
128  gt1_rxcommadet_out : out std_logic;
130  gt1_rxchariscomma_out : out std_logic_vector(3 downto 0);
131  gt1_rxcharisk_out : out std_logic_vector(3 downto 0);
133  gt1_rxresetdone_out : out std_logic;
135  gt1_txdata_in : in std_logic_vector(31 downto 0);
137  gt1_txresetdone_out : out std_logic;
139  gt1_txcharisk_in : in std_logic_vector(3 downto 0);
141  gt1_txbufstatus_out : out std_logic_vector(1 downto 0);
142 
143  --GT2 (X0Y2)________________________________
144  --____________________________CHANNEL PORTS________________________________
146  gt2_loopback_in : in std_logic_vector(2 downto 0);
148  gt2_rxpd_in : in std_logic_vector(1 downto 0);
149  gt2_txpd_in : in std_logic_vector(1 downto 0);
151  gt2_rxdata_out : out std_logic_vector(31 downto 0);
153  gt2_rxdisperr_out : out std_logic_vector(3 downto 0);
154  gt2_rxnotintable_out : out std_logic_vector(3 downto 0);
156  gt2_rxbyteisaligned_out : out std_logic;
157  gt2_rxbyterealign_out : out std_logic;
158  gt2_rxcommadet_out : out std_logic;
160  gt2_rxchariscomma_out : out std_logic_vector(3 downto 0);
161  gt2_rxcharisk_out : out std_logic_vector(3 downto 0);
163  gt2_rxresetdone_out : out std_logic;
165  gt2_txdata_in : in std_logic_vector(31 downto 0);
167  gt2_txresetdone_out : out std_logic;
169  gt2_txcharisk_in : in std_logic_vector(3 downto 0);
171  gt2_txbufstatus_out : out std_logic_vector(1 downto 0);
172 
173  --GT3 (X0Y3)
174  --____________________________CHANNEL PORTS________________________________
176  gt3_loopback_in : in std_logic_vector(2 downto 0);
178  gt3_rxpd_in : in std_logic_vector(1 downto 0);
179  gt3_txpd_in : in std_logic_vector(1 downto 0);
181  gt3_rxdata_out : out std_logic_vector(31 downto 0);
183  gt3_rxdisperr_out : out std_logic_vector(3 downto 0);
184  gt3_rxnotintable_out : out std_logic_vector(3 downto 0);
186  gt3_rxbyteisaligned_out : out std_logic;
187  gt3_rxbyterealign_out : out std_logic;
188  gt3_rxcommadet_out : out std_logic;
190  gt3_rxchariscomma_out : out std_logic_vector(3 downto 0);
191  gt3_rxcharisk_out : out std_logic_vector(3 downto 0);
193  gt3_rxresetdone_out : out std_logic;
195  gt3_txdata_in : in std_logic_vector(31 downto 0);
197  gt3_txresetdone_out : out std_logic;
199  gt3_txcharisk_in : in std_logic_vector(3 downto 0);
201  gt3_txbufstatus_out : out std_logic_vector(1 downto 0);
202 
204  GT0_QPLLLOCK_OUT : out std_logic;
205  GT0_QPLLREFCLKLOST_OUT : out std_logic;
206  sysclk_in : in std_logic
207 
208  );
209 
210 
211 end mgt_selection_wrapper;
213 
214 architecture RTL of mgt_selection_wrapper is
215 
216 
217 -- attribute DowngradeIPIdentifiedWarnings : string;
218 -- attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
219 
220 -- attribute CORE_GENERATION_INFO : string;
221 -- attribute CORE_GENERATION_INFO of RTL : architecture is "min_latency_1_quad_rx_tx,gtwizard_v3_6_5,{protocol_file=Start_from_scratch}";
222 
223 ----**************************Component Declarations*****************************
224 
225 
226 
227 -- signal tied_to_ground_i : std_logic;
228 -- signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
229 -- signal tied_to_vcc_i : std_logic;
230 -- signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
231 
232 --**************************** Main Body of Code *******************************
233 
234 begin
235 
236 -- -- Static signal Assigments
237 -- tied_to_ground_i <= '0';
238 -- tied_to_ground_vec_i <= x"0000000000000000";
239 -- tied_to_vcc_i <= '1';
240 -- tied_to_vcc_vec_i <= "11111111";
241 
242 
243  ----------------------------- The GT Wrapper -----------------------------
244 
245  -- Use the instantiation template in the example directory to add the GT wrapper to your design.
246  -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
247  -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
248  -- enabled, bonding should occur after alignment.
249 
250  QUAD_ENABLED : if ENABLED = '1' generate
251  mgt: entity work.min_latency_1quad_11g2_RxTX_wrapper
252  generic map (
253  EXAMPLE_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
254  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD)
255  port map (
256  clk280 => clk280,
257  SOFT_RESET_TX_IN => SOFT_RESET_TX_IN,
258  SOFT_RESET_RX_IN => SOFT_RESET_RX_IN,
259  RXN_IN => RXN_IN,
260  RXP_IN => RXP_IN,
261  TXN_OUT => TXN_OUT,
262  TXP_OUT => TXP_OUT,
263  Q0_CLK0_GTREFCLK_PAD_N_IN => Q0_CLK0_GTREFCLK_PAD_N_IN,
264  Q0_CLK0_GTREFCLK_PAD_P_IN => Q0_CLK0_GTREFCLK_PAD_P_IN,
265  GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT,
266  GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE_OUT,
267  GT0_DATA_VALID_IN => GT0_DATA_VALID_IN,
268  GT1_TX_FSM_RESET_DONE_OUT => GT1_TX_FSM_RESET_DONE_OUT,
269  GT1_RX_FSM_RESET_DONE_OUT => GT1_RX_FSM_RESET_DONE_OUT,
270  GT1_DATA_VALID_IN => GT1_DATA_VALID_IN,
271  GT2_TX_FSM_RESET_DONE_OUT => GT2_TX_FSM_RESET_DONE_OUT,
272  GT2_RX_FSM_RESET_DONE_OUT => GT2_RX_FSM_RESET_DONE_OUT,
273  GT2_DATA_VALID_IN => GT2_DATA_VALID_IN,
274  GT3_TX_FSM_RESET_DONE_OUT => GT3_TX_FSM_RESET_DONE_OUT,
275  GT3_RX_FSM_RESET_DONE_OUT => GT3_RX_FSM_RESET_DONE_OUT,
276  GT3_DATA_VALID_IN => GT3_DATA_VALID_IN,
277  GT0_TXUSRCLK_OUT => GT0_TXUSRCLK_OUT,
278  GT0_RXUSRCLK_OUT => GT0_RXUSRCLK_OUT,
279  GT1_TXUSRCLK_OUT => GT1_TXUSRCLK_OUT,
280  GT1_RXUSRCLK_OUT => GT1_RXUSRCLK_OUT,
281  GT2_TXUSRCLK_OUT => GT2_TXUSRCLK_OUT,
282  GT2_RXUSRCLK_OUT => GT2_RXUSRCLK_OUT,
283  GT3_TXUSRCLK_OUT => GT3_TXUSRCLK_OUT,
284  GT3_RXUSRCLK_OUT => GT3_RXUSRCLK_OUT,
285  gt0_loopback_in => gt0_loopback_in,
286  gt0_rxpd_in => gt0_rxpd_in,
287  gt0_txpd_in => gt0_txpd_in,
288  gt0_rxdata_out => gt0_rxdata_out,
289  gt0_rxdisperr_out => gt0_rxdisperr_out,
290  gt0_rxnotintable_out => gt0_rxnotintable_out,
291  gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
292  gt0_rxbyterealign_out => gt0_rxbyterealign_out,
293  gt0_rxcommadet_out => gt0_rxcommadet_out,
294  gt0_rxchariscomma_out => gt0_rxchariscomma_out,
295  gt0_rxcharisk_out => gt0_rxcharisk_out,
296  gt0_rxresetdone_out => gt0_rxresetdone_out,
297  gt0_txdata_in => gt0_txdata_in,
298  gt0_txresetdone_out => gt0_txresetdone_out,
299  gt0_txcharisk_in => gt0_txcharisk_in,
300  gt0_txbufstatus_out => gt0_txbufstatus_out,
301  gt1_loopback_in => gt1_loopback_in,
302  gt1_rxpd_in => gt1_rxpd_in,
303  gt1_txpd_in => gt1_txpd_in,
304  gt1_rxdata_out => gt1_rxdata_out,
305  gt1_rxdisperr_out => gt1_rxdisperr_out,
306  gt1_rxnotintable_out => gt1_rxnotintable_out,
307  gt1_rxbyteisaligned_out => gt1_rxbyteisaligned_out,
308  gt1_rxbyterealign_out => gt1_rxbyterealign_out,
309  gt1_rxcommadet_out => gt1_rxcommadet_out,
310  gt1_rxchariscomma_out => gt1_rxchariscomma_out,
311  gt1_rxcharisk_out => gt1_rxcharisk_out,
312  gt1_rxresetdone_out => gt1_rxresetdone_out,
313  gt1_txdata_in => gt1_txdata_in,
314  gt1_txresetdone_out => gt1_txresetdone_out,
315  gt1_txcharisk_in => gt1_txcharisk_in,
316  gt1_txbufstatus_out => gt1_txbufstatus_out,
317  gt2_loopback_in => gt2_loopback_in,
318  gt2_rxpd_in => gt2_rxpd_in,
319  gt2_txpd_in => gt2_txpd_in,
320  gt2_rxdata_out => gt2_rxdata_out,
321  gt2_rxdisperr_out => gt2_rxdisperr_out,
322  gt2_rxnotintable_out => gt2_rxnotintable_out,
323  gt2_rxbyteisaligned_out => gt2_rxbyteisaligned_out,
324  gt2_rxbyterealign_out => gt2_rxbyterealign_out,
325  gt2_rxcommadet_out => gt2_rxcommadet_out,
326  gt2_rxchariscomma_out => gt2_rxchariscomma_out,
327  gt2_rxcharisk_out => gt2_rxcharisk_out,
328  gt2_rxresetdone_out => gt2_rxresetdone_out,
329  gt2_txdata_in => gt2_txdata_in,
330  gt2_txresetdone_out => gt2_txresetdone_out,
331  gt2_txcharisk_in => gt2_txcharisk_in,
332  gt2_txbufstatus_out => gt2_txbufstatus_out,
333  gt3_loopback_in => gt3_loopback_in,
334  gt3_rxpd_in => gt3_rxpd_in,
335  gt3_txpd_in => gt3_txpd_in,
336  gt3_rxdata_out => gt3_rxdata_out,
337  gt3_rxdisperr_out => gt3_rxdisperr_out,
338  gt3_rxnotintable_out => gt3_rxnotintable_out,
339  gt3_rxbyteisaligned_out => gt3_rxbyteisaligned_out,
340  gt3_rxbyterealign_out => gt3_rxbyterealign_out,
341  gt3_rxcommadet_out => gt3_rxcommadet_out,
342  gt3_rxchariscomma_out => gt3_rxchariscomma_out,
343  gt3_rxcharisk_out => gt3_rxcharisk_out,
344  gt3_rxresetdone_out => gt3_rxresetdone_out,
345  gt3_txdata_in => gt3_txdata_in,
346  gt3_txresetdone_out => gt3_txresetdone_out,
347  gt3_txcharisk_in => gt3_txcharisk_in,
348  gt3_txbufstatus_out => gt3_txbufstatus_out,
349  GT0_QPLLLOCK_OUT => GT0_QPLLLOCK_OUT,
350  GT0_QPLLREFCLKLOST_OUT => GT0_QPLLREFCLKLOST_OUT,
351  sysclk_in => sysclk_in);
352  end generate;
353 
354  QUAD_DISABLED : if ENABLED = '0' generate
355  TXN_OUT <= (others => '0');
356  TXP_OUT <= (others => '0');
357  GT0_TX_FSM_RESET_DONE_OUT <= '0';
358  GT0_RX_FSM_RESET_DONE_OUT <= '0';
359  GT1_TX_FSM_RESET_DONE_OUT <= '0';
360  GT1_RX_FSM_RESET_DONE_OUT <= '0';
361  GT2_TX_FSM_RESET_DONE_OUT <= '0';
362  GT2_RX_FSM_RESET_DONE_OUT <= '0';
363  GT3_TX_FSM_RESET_DONE_OUT <= '0';
364  GT3_RX_FSM_RESET_DONE_OUT <= '0';
365  GT0_TXUSRCLK_OUT <= '0';
366  GT0_RXUSRCLK_OUT <= '0';
367  GT1_TXUSRCLK_OUT <= '0';
368  GT1_RXUSRCLK_OUT <= '0';
369  GT2_TXUSRCLK_OUT <= '0';
370  GT2_RXUSRCLK_OUT <= '0';
371  GT3_TXUSRCLK_OUT <= '0';
372  GT3_RXUSRCLK_OUT <= '0';
373  gt0_rxdata_out <= (others => '0');
374  gt0_rxdisperr_out <= (others => '0');
375  gt0_rxnotintable_out <= (others => '0');
376  gt0_rxbyteisaligned_out <= '0';
377  gt0_rxbyterealign_out <= '0';
378  gt0_rxcommadet_out <= '0';
379  gt0_rxchariscomma_out <= (others => '0');
380  gt0_rxcharisk_out <= (others => '0');
381  gt0_rxresetdone_out <= '0';
382  gt0_txresetdone_out <= '0';
383  gt0_txbufstatus_out <= (others => '0');
384  gt1_rxdata_out <= (others => '0');
385  gt1_rxdisperr_out <= (others => '0');
386  gt1_rxnotintable_out <= (others => '0');
387  gt1_rxbyteisaligned_out <= '0';
388  gt1_rxbyterealign_out <= '0';
389  gt1_rxcommadet_out <= '0';
390  gt1_rxchariscomma_out <= (others => '0');
391  gt1_rxcharisk_out <= (others => '0');
392  gt1_rxresetdone_out <= '0';
393  gt1_txresetdone_out <= '0';
394  gt1_txbufstatus_out <= (others => '0');
395 
396  gt2_rxdata_out <= (others => '0');
397  gt2_rxdisperr_out <= (others => '0');
398  gt2_rxnotintable_out <= (others => '0');
399  gt2_rxbyteisaligned_out <= '0';
400  gt2_rxbyterealign_out <= '0';
401  gt2_rxcommadet_out <= '0';
402  gt2_rxchariscomma_out <= (others => '0');
403  gt2_rxcharisk_out <= (others => '0');
404  gt2_rxresetdone_out <= '0';
405  gt2_txresetdone_out <= '0';
406  gt2_txbufstatus_out <= (others => '0');
407  gt3_rxdata_out <= (others => '0');
408  gt3_rxdisperr_out <= (others => '0');
409  gt3_rxnotintable_out <= (others => '0');
410  gt3_rxbyteisaligned_out <= '0';
411  gt3_rxbyterealign_out <= '0';
412  gt3_rxcommadet_out <= '0';
413  gt3_rxchariscomma_out <= (others => '0');
414  gt3_rxcharisk_out <= (others => '0');
415  gt3_rxresetdone_out <= '0';
416  gt3_txresetdone_out <= '0';
417  gt3_txbufstatus_out <= (others => '0');
418  GT0_QPLLLOCK_OUT <= '0';
419  GT0_QPLLREFCLKLOST_OUT <= '0';
420  end generate;
421 end RTL;
422 
mgt_selection_wrapper.RTL
mgt selection wrapper
Definition: mgt_selection_wrapper.vhd:214
mgt_selection_wrapper
mgt selection wrapper
Definition: mgt_selection_wrapper.vhd:15
mgt_selection_wrapper.gt1_rxdata_out
out gt1_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt1.
Definition: mgt_selection_wrapper.vhd:121
mgt_selection_wrapper.gt3_txbufstatus_out
out gt3_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt3.
Definition: mgt_selection_wrapper.vhd:201
mgt_selection_wrapper.gt3_rxbyteisaligned_out
out gt3_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt3.
Definition: mgt_selection_wrapper.vhd:186
mgt_selection_wrapper.gt2_txresetdone_out
out gt2_txresetdone_out std_logic
Transmit Ports - TX Fabric Clock Output Control Ports for gt2.
Definition: mgt_selection_wrapper.vhd:167
mgt_selection_wrapper.GT3_DATA_VALID_IN
in GT3_DATA_VALID_IN std_logic
status of data valid in not used gt3
Definition: mgt_selection_wrapper.vhd:63
mgt_selection_wrapper.gt1_txdata_in
in gt1_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface gt1.
Definition: mgt_selection_wrapper.vhd:135
mgt_selection_wrapper.GT0_TXUSRCLK_OUT
out GT0_TXUSRCLK_OUT std_logic
tx user clock out gt0
Definition: mgt_selection_wrapper.vhd:65
mgt_selection_wrapper.gt0_txbufstatus_out
out gt0_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt0.
Definition: mgt_selection_wrapper.vhd:110
mgt_selection_wrapper.TXN_OUT
out TXN_OUT std_logic_vector( 3 downto 0)
tx quad output
Definition: mgt_selection_wrapper.vhd:35
mgt_selection_wrapper.gt0_rxdisperr_out
out gt0_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt0.
Definition: mgt_selection_wrapper.vhd:92
mgt_selection_wrapper.GT3_TX_FSM_RESET_DONE_OUT
out GT3_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt3
Definition: mgt_selection_wrapper.vhd:59
mgt_selection_wrapper.GT2_RX_FSM_RESET_DONE_OUT
out GT2_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt2
Definition: mgt_selection_wrapper.vhd:55
mgt_selection_wrapper.GT0_DATA_VALID_IN
in GT0_DATA_VALID_IN std_logic
status of data valid in not used gt0
Definition: mgt_selection_wrapper.vhd:45
mgt_selection_wrapper.GT0_QPLLLOCK_OUT
out GT0_QPLLLOCK_OUT std_logic
COMMON PORTS.
Definition: mgt_selection_wrapper.vhd:204
mgt_selection_wrapper.gt2_rxresetdone_out
out gt2_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt2.
Definition: mgt_selection_wrapper.vhd:163
mgt_selection_wrapper.gt2_rxpd_in
in gt2_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt2.
Definition: mgt_selection_wrapper.vhd:148
mgt_selection_wrapper.gt1_txbufstatus_out
out gt1_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt1.
Definition: mgt_selection_wrapper.vhd:141
mgt_selection_wrapper.gt0_rxdata_out
out gt0_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt0.
Definition: mgt_selection_wrapper.vhd:90
mgt_selection_wrapper.GT2_TXUSRCLK_OUT
out GT2_TXUSRCLK_OUT std_logic
tx user clock out gt2
Definition: mgt_selection_wrapper.vhd:73
mgt_selection_wrapper.gt3_rxdisperr_out
out gt3_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt3.
Definition: mgt_selection_wrapper.vhd:183
mgt_selection_wrapper.gt2_loopback_in
in gt2_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt2.
Definition: mgt_selection_wrapper.vhd:146
mgt_selection_wrapper.gt1_rxresetdone_out
out gt1_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt1.
Definition: mgt_selection_wrapper.vhd:133
mgt_selection_wrapper.gt0_txdata_in
in gt0_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface gt0.
Definition: mgt_selection_wrapper.vhd:104
mgt_selection_wrapper.gt3_rxdata_out
out gt3_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt3.
Definition: mgt_selection_wrapper.vhd:181
mgt_selection_wrapper.gt2_rxbyteisaligned_out
out gt2_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt2.
Definition: mgt_selection_wrapper.vhd:156
mgt_selection_wrapper.gt3_loopback_in
in gt3_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt3.
Definition: mgt_selection_wrapper.vhd:176
mgt_selection_wrapper.GT1_RX_FSM_RESET_DONE_OUT
out GT1_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt1
Definition: mgt_selection_wrapper.vhd:49
mgt_selection_wrapper.gt0_rxchariscomma_out
out gt0_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt0.
Definition: mgt_selection_wrapper.vhd:99
mgt_selection_wrapper.gt0_txresetdone_out
out gt0_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt0.
Definition: mgt_selection_wrapper.vhd:106
mgt_selection_wrapper.GT3_TXUSRCLK_OUT
out GT3_TXUSRCLK_OUT std_logic
tx user clock out gt3
Definition: mgt_selection_wrapper.vhd:77
mgt_selection_wrapper.GT3_RX_FSM_RESET_DONE_OUT
out GT3_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt3
Definition: mgt_selection_wrapper.vhd:61
mgt_selection_wrapper.gt2_rxdisperr_out
out gt2_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt2.
Definition: mgt_selection_wrapper.vhd:153
mgt_selection_wrapper.GT1_DATA_VALID_IN
in GT1_DATA_VALID_IN std_logic
status of data valid in not used gt1
Definition: mgt_selection_wrapper.vhd:51
mgt_selection_wrapper.gt0_rxresetdone_out
out gt0_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt0.
Definition: mgt_selection_wrapper.vhd:102
mgt_selection_wrapper.gt3_txdata_in
in gt3_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt3.
Definition: mgt_selection_wrapper.vhd:195
mgt_selection_wrapper.gt3_rxresetdone_out
out gt3_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt3.
Definition: mgt_selection_wrapper.vhd:193
mgt_selection_wrapper.gt2_txbufstatus_out
out gt2_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt2.
Definition: mgt_selection_wrapper.vhd:171
mgt_selection_wrapper.gt3_txcharisk_in
in gt3_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt3.
Definition: mgt_selection_wrapper.vhd:199
mgt_selection_wrapper.clk280
in clk280 std_logic
fabric clock of 280MHz
Definition: mgt_selection_wrapper.vhd:26
mgt_selection_wrapper.gt0_rxpd_in
in gt0_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt0.
Definition: mgt_selection_wrapper.vhd:87
mgt_selection_wrapper.gt2_rxchariscomma_out
out gt2_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt2.
Definition: mgt_selection_wrapper.vhd:160
mgt_selection_wrapper.GT3_RXUSRCLK_OUT
out GT3_RXUSRCLK_OUT std_logic
rx user clock out gt3
Definition: mgt_selection_wrapper.vhd:79
mgt_selection_wrapper.gt0_rxbyteisaligned_out
out gt0_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt0.
Definition: mgt_selection_wrapper.vhd:95
mgt_selection_wrapper.GT0_TX_FSM_RESET_DONE_OUT
out GT0_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt0
Definition: mgt_selection_wrapper.vhd:41
mgt_selection_wrapper.SOFT_RESET_TX_IN
in SOFT_RESET_TX_IN std_logic
soft reset of tx quad
Definition: mgt_selection_wrapper.vhd:28
mgt_selection_wrapper.GT1_RXUSRCLK_OUT
out GT1_RXUSRCLK_OUT std_logic
rx user clock out gt1
Definition: mgt_selection_wrapper.vhd:71
mgt_selection_wrapper.gt1_txresetdone_out
out gt1_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt1.
Definition: mgt_selection_wrapper.vhd:137
mgt_selection_wrapper.gt1_txcharisk_in
in gt1_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt1.
Definition: mgt_selection_wrapper.vhd:139
mgt_selection_wrapper.gt1_rxpd_in
in gt1_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt1.
Definition: mgt_selection_wrapper.vhd:118
mgt_selection_wrapper.gt1_rxbyteisaligned_out
out gt1_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt1.
Definition: mgt_selection_wrapper.vhd:126
mgt_selection_wrapper.RXN_IN
in RXN_IN std_logic_vector( 3 downto 0)
rx quad input
Definition: mgt_selection_wrapper.vhd:32
mgt_selection_wrapper.GT2_RXUSRCLK_OUT
out GT2_RXUSRCLK_OUT std_logic
rx user clock out gt2
Definition: mgt_selection_wrapper.vhd:75
mgt_selection_wrapper.gt1_rxchariscomma_out
out gt1_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt1.
Definition: mgt_selection_wrapper.vhd:130
mgt_selection_wrapper.gt2_rxdata_out
out gt2_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt2.
Definition: mgt_selection_wrapper.vhd:151
mgt_selection_wrapper.gt3_rxpd_in
in gt3_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt3.
Definition: mgt_selection_wrapper.vhd:178
mgt_selection_wrapper.Q0_CLK0_GTREFCLK_PAD_N_IN
in Q0_CLK0_GTREFCLK_PAD_N_IN std_logic
clock input to the quad
Definition: mgt_selection_wrapper.vhd:38
mgt_selection_wrapper.gt2_txcharisk_in
in gt2_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt2.
Definition: mgt_selection_wrapper.vhd:169
mgt_selection_wrapper.gt3_rxchariscomma_out
out gt3_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt3.
Definition: mgt_selection_wrapper.vhd:190
mgt_selection_wrapper.gt2_txdata_in
in gt2_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt2.
Definition: mgt_selection_wrapper.vhd:165
mgt_selection_wrapper.GT2_TX_FSM_RESET_DONE_OUT
out GT2_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt2
Definition: mgt_selection_wrapper.vhd:53
mgt_selection_wrapper.gt1_loopback_in
in gt1_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt1.
Definition: mgt_selection_wrapper.vhd:116
mgt_selection_wrapper.gt0_txcharisk_in
in gt0_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports gt0.
Definition: mgt_selection_wrapper.vhd:108
mgt_selection_wrapper.GT0_RXUSRCLK_OUT
out GT0_RXUSRCLK_OUT std_logic
rx user clock out gt0
Definition: mgt_selection_wrapper.vhd:67
mgt_selection_wrapper.GT0_RX_FSM_RESET_DONE_OUT
out GT0_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gto
Definition: mgt_selection_wrapper.vhd:43
mgt_selection_wrapper.GT2_DATA_VALID_IN
in GT2_DATA_VALID_IN std_logic
status of data valid in not used gt2
Definition: mgt_selection_wrapper.vhd:57
mgt_selection_wrapper.gt1_rxdisperr_out
out gt1_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt1.
Definition: mgt_selection_wrapper.vhd:123
mgt_selection_wrapper.gt3_txresetdone_out
out gt3_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt3.
Definition: mgt_selection_wrapper.vhd:197
mgt_selection_wrapper.SOFT_RESET_RX_IN
in SOFT_RESET_RX_IN std_logic
soft reset of rx quad
Definition: mgt_selection_wrapper.vhd:30
mgt_selection_wrapper.gt0_loopback_in
in gt0_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt0.
Definition: mgt_selection_wrapper.vhd:85
mgt_selection_wrapper.GT1_TX_FSM_RESET_DONE_OUT
out GT1_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt1
Definition: mgt_selection_wrapper.vhd:47
mgt_selection_wrapper.GT1_TXUSRCLK_OUT
out GT1_TXUSRCLK_OUT std_logic
tx user clock out gt1
Definition: mgt_selection_wrapper.vhd:69
min_latency_1quad_11g2_RxTX_wrapper
Quad MGT wrapper.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:16
min_latency_1quad_11g2_RxTX_wrapper.gt1_rxdata_out
out gt1_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt1.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:121
min_latency_1quad_11g2_RxTX_wrapper.gt3_txbufstatus_out
out gt3_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt3.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:201
min_latency_1quad_11g2_RxTX_wrapper.gt3_rxbyteisaligned_out
out gt3_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt3.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:186
min_latency_1quad_11g2_RxTX_wrapper.gt2_txresetdone_out
out gt2_txresetdone_out std_logic
Transmit Ports - TX Fabric Clock Output Control Ports for gt2.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:167
min_latency_1quad_11g2_RxTX_wrapper.GT3_DATA_VALID_IN
in GT3_DATA_VALID_IN std_logic
status of data valid in not used gt3
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:63
min_latency_1quad_11g2_RxTX_wrapper.gt1_txdata_in
in gt1_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface gt1.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:135
min_latency_1quad_11g2_RxTX_wrapper.GT0_TXUSRCLK_OUT
out GT0_TXUSRCLK_OUT std_logic
tx user clock out gt0
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:65
min_latency_1quad_11g2_RxTX_wrapper.gt0_txbufstatus_out
out gt0_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt0.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:110
min_latency_1quad_11g2_RxTX_wrapper.TXN_OUT
out TXN_OUT std_logic_vector( 3 downto 0)
tx quad output
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:35
min_latency_1quad_11g2_RxTX_wrapper.gt0_rxdisperr_out
out gt0_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt0.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:92
min_latency_1quad_11g2_RxTX_wrapper.GT3_TX_FSM_RESET_DONE_OUT
out GT3_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt3
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:59
min_latency_1quad_11g2_RxTX_wrapper.GT2_RX_FSM_RESET_DONE_OUT
out GT2_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt2
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:55
min_latency_1quad_11g2_RxTX_wrapper.GT0_DATA_VALID_IN
in GT0_DATA_VALID_IN std_logic
status of data valid in not used gt0
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:45
min_latency_1quad_11g2_RxTX_wrapper.GT0_QPLLLOCK_OUT
out GT0_QPLLLOCK_OUT std_logic
COMMON PORTS.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:204
min_latency_1quad_11g2_RxTX_wrapper.gt2_rxresetdone_out
out gt2_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt2.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:163
min_latency_1quad_11g2_RxTX_wrapper.gt2_rxpd_in
in gt2_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt2.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:148
min_latency_1quad_11g2_RxTX_wrapper.gt1_txbufstatus_out
out gt1_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt1.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:141
min_latency_1quad_11g2_RxTX_wrapper.gt0_rxdata_out
out gt0_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt0.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:90
min_latency_1quad_11g2_RxTX_wrapper.GT2_TXUSRCLK_OUT
out GT2_TXUSRCLK_OUT std_logic
tx user clock out gt2
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:73
min_latency_1quad_11g2_RxTX_wrapper.gt3_rxdisperr_out
out gt3_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt3.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:183
min_latency_1quad_11g2_RxTX_wrapper.gt2_loopback_in
in gt2_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt2.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:146
min_latency_1quad_11g2_RxTX_wrapper.gt1_rxresetdone_out
out gt1_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt1.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:133
min_latency_1quad_11g2_RxTX_wrapper.gt0_txdata_in
in gt0_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface gt0.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:104
min_latency_1quad_11g2_RxTX_wrapper.gt3_rxdata_out
out gt3_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt3.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:181
min_latency_1quad_11g2_RxTX_wrapper.gt2_rxbyteisaligned_out
out gt2_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt2.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:156
min_latency_1quad_11g2_RxTX_wrapper.gt3_loopback_in
in gt3_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt3.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:176
min_latency_1quad_11g2_RxTX_wrapper.GT1_RX_FSM_RESET_DONE_OUT
out GT1_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt1
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:49
min_latency_1quad_11g2_RxTX_wrapper.gt0_rxchariscomma_out
out gt0_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt0.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:99
min_latency_1quad_11g2_RxTX_wrapper.gt0_txresetdone_out
out gt0_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt0.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:106
min_latency_1quad_11g2_RxTX_wrapper.GT3_TXUSRCLK_OUT
out GT3_TXUSRCLK_OUT std_logic
tx user clock out gt3
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:77
min_latency_1quad_11g2_RxTX_wrapper.GT3_RX_FSM_RESET_DONE_OUT
out GT3_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt3
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:61
min_latency_1quad_11g2_RxTX_wrapper.gt2_rxdisperr_out
out gt2_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt2.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:153
min_latency_1quad_11g2_RxTX_wrapper.GT1_DATA_VALID_IN
in GT1_DATA_VALID_IN std_logic
status of data valid in not used gt1
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:51
min_latency_1quad_11g2_RxTX_wrapper.gt0_rxresetdone_out
out gt0_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt0.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:102
min_latency_1quad_11g2_RxTX_wrapper.gt3_txdata_in
in gt3_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt3.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:195
min_latency_1quad_11g2_RxTX_wrapper.gt3_rxresetdone_out
out gt3_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt3.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:193
min_latency_1quad_11g2_RxTX_wrapper.gt2_txbufstatus_out
out gt2_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt2.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:171
min_latency_1quad_11g2_RxTX_wrapper.gt3_txcharisk_in
in gt3_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt3.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:199
min_latency_1quad_11g2_RxTX_wrapper.clk280
in clk280 std_logic
fabric clock of 280MHz
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:26
min_latency_1quad_11g2_RxTX_wrapper.gt0_rxpd_in
in gt0_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt0.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:87
min_latency_1quad_11g2_RxTX_wrapper.gt2_rxchariscomma_out
out gt2_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt2.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:160
min_latency_1quad_11g2_RxTX_wrapper.GT3_RXUSRCLK_OUT
out GT3_RXUSRCLK_OUT std_logic
rx user clock out gt3
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:79
min_latency_1quad_11g2_RxTX_wrapper.gt0_rxbyteisaligned_out
out gt0_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt0.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:95
min_latency_1quad_11g2_RxTX_wrapper.GT0_TX_FSM_RESET_DONE_OUT
out GT0_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt0
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:41
min_latency_1quad_11g2_RxTX_wrapper.SOFT_RESET_TX_IN
in SOFT_RESET_TX_IN std_logic
soft reset of tx quad
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:28
min_latency_1quad_11g2_RxTX_wrapper.GT1_RXUSRCLK_OUT
out GT1_RXUSRCLK_OUT std_logic
rx user clock out gt1
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:71
min_latency_1quad_11g2_RxTX_wrapper.gt1_txresetdone_out
out gt1_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt1.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:137
min_latency_1quad_11g2_RxTX_wrapper.gt1_txcharisk_in
in gt1_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt1.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:139
min_latency_1quad_11g2_RxTX_wrapper.gt1_rxpd_in
in gt1_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt1.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:118
min_latency_1quad_11g2_RxTX_wrapper.gt1_rxbyteisaligned_out
out gt1_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt1.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:126
min_latency_1quad_11g2_RxTX_wrapper.RXN_IN
in RXN_IN std_logic_vector( 3 downto 0)
rx quad input
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:32
min_latency_1quad_11g2_RxTX_wrapper.GT2_RXUSRCLK_OUT
out GT2_RXUSRCLK_OUT std_logic
rx user clock out gt2
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:75
min_latency_1quad_11g2_RxTX_wrapper.gt1_rxchariscomma_out
out gt1_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt1.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:130
min_latency_1quad_11g2_RxTX_wrapper.gt2_rxdata_out
out gt2_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt2.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:151
min_latency_1quad_11g2_RxTX_wrapper.gt3_rxpd_in
in gt3_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt3.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:178
min_latency_1quad_11g2_RxTX_wrapper.Q0_CLK0_GTREFCLK_PAD_N_IN
in Q0_CLK0_GTREFCLK_PAD_N_IN std_logic
clock input to the quad
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:38
min_latency_1quad_11g2_RxTX_wrapper.gt2_txcharisk_in
in gt2_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt2.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:169
min_latency_1quad_11g2_RxTX_wrapper.gt3_rxchariscomma_out
out gt3_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt3.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:190
min_latency_1quad_11g2_RxTX_wrapper.gt2_txdata_in
in gt2_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt2.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:165
min_latency_1quad_11g2_RxTX_wrapper.GT2_TX_FSM_RESET_DONE_OUT
out GT2_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt2
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:53
min_latency_1quad_11g2_RxTX_wrapper.gt1_loopback_in
in gt1_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt1.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:116
min_latency_1quad_11g2_RxTX_wrapper.gt0_txcharisk_in
in gt0_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports gt0.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:108
min_latency_1quad_11g2_RxTX_wrapper.GT0_RXUSRCLK_OUT
out GT0_RXUSRCLK_OUT std_logic
rx user clock out gt0
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:67
min_latency_1quad_11g2_RxTX_wrapper.GT0_RX_FSM_RESET_DONE_OUT
out GT0_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gto
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:43
min_latency_1quad_11g2_RxTX_wrapper.GT2_DATA_VALID_IN
in GT2_DATA_VALID_IN std_logic
status of data valid in not used gt2
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:57
min_latency_1quad_11g2_RxTX_wrapper.gt1_rxdisperr_out
out gt1_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt1.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:123
min_latency_1quad_11g2_RxTX_wrapper.gt3_txresetdone_out
out gt3_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt3.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:197
min_latency_1quad_11g2_RxTX_wrapper.SOFT_RESET_RX_IN
in SOFT_RESET_RX_IN std_logic
soft reset of rx quad
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:30
min_latency_1quad_11g2_RxTX_wrapper.gt0_loopback_in
in gt0_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt0.
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:85
min_latency_1quad_11g2_RxTX_wrapper.GT1_TX_FSM_RESET_DONE_OUT
out GT1_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt1
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:47
min_latency_1quad_11g2_RxTX_wrapper.GT1_TXUSRCLK_OUT
out GT1_TXUSRCLK_OUT std_logic
tx user clock out gt1
Definition: min_latency_1quad_11g2_RxTX_wrapper.vhd:69
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