min_latency_1quad_11g2_RxTX_wrapper Entity Reference

Quad MGT wrapper. More...

Inheritance diagram for min_latency_1quad_11g2_RxTX_wrapper:

Entities
RTL	architecture
	Quad MGT wrapper. More...

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
std_logic_unsigned
VCOMPONENTS

Generics
EXAMPLE_SIM_GTRESET_SPEEDUP	string := " TRUE "
STABLE_CLOCK_PERIOD	integer := 16

Ports
clk280	in	std_logic
		fabric clock of 280MHz
SOFT_RESET_TX_IN	in	std_logic
		soft reset of tx quad
SOFT_RESET_RX_IN	in	std_logic
		soft reset of rx quad
RXN_IN	in	std_logic_vector ( 3 downto 0 )
		rx quad input
RXP_IN	in	std_logic_vector ( 3 downto 0 )
TXN_OUT	out	std_logic_vector ( 3 downto 0 )
		tx quad output
TXP_OUT	out	std_logic_vector ( 3 downto 0 )
Q0_CLK0_GTREFCLK_PAD_N_IN	in	std_logic
		clock input to the quad
Q0_CLK0_GTREFCLK_PAD_P_IN	in	std_logic
GT0_TX_FSM_RESET_DONE_OUT	out	std_logic
		status reset of the tx fsm gt0
GT0_RX_FSM_RESET_DONE_OUT	out	std_logic
		status reset of the rx fsm gto
GT0_DATA_VALID_IN	in	std_logic
		status of data valid in not used gt0
GT1_TX_FSM_RESET_DONE_OUT	out	std_logic
		status reset of the tx fsm gt1
GT1_RX_FSM_RESET_DONE_OUT	out	std_logic
		status reset of the rx fsm gt1
GT1_DATA_VALID_IN	in	std_logic
		status of data valid in not used gt1
GT2_TX_FSM_RESET_DONE_OUT	out	std_logic
		status reset of the tx fsm gt2
GT2_RX_FSM_RESET_DONE_OUT	out	std_logic
		status reset of the rx fsm gt2
GT2_DATA_VALID_IN	in	std_logic
		status of data valid in not used gt2
GT3_TX_FSM_RESET_DONE_OUT	out	std_logic
		status reset of the tx fsm gt3
GT3_RX_FSM_RESET_DONE_OUT	out	std_logic
		status reset of the rx fsm gt3
GT3_DATA_VALID_IN	in	std_logic
		status of data valid in not used gt3
GT0_TXUSRCLK_OUT	out	std_logic
		tx user clock out gt0
GT0_RXUSRCLK_OUT	out	std_logic
		rx user clock out gt0
GT1_TXUSRCLK_OUT	out	std_logic
		tx user clock out gt1
GT1_RXUSRCLK_OUT	out	std_logic
		rx user clock out gt1
GT2_TXUSRCLK_OUT	out	std_logic
		tx user clock out gt2
GT2_RXUSRCLK_OUT	out	std_logic
		rx user clock out gt2
GT3_TXUSRCLK_OUT	out	std_logic
		tx user clock out gt3
GT3_RXUSRCLK_OUT	out	std_logic
		rx user clock out gt3
gt0_loopback_in	in	std_logic_vector ( 2 downto 0 )
		Loopback Ports for gt0.
gt0_rxpd_in	in	std_logic_vector ( 1 downto 0 )
		Power-Down Ports for gt0.
gt0_txpd_in	in	std_logic_vector ( 1 downto 0 )
gt0_rxdata_out	out	std_logic_vector ( 31 downto 0 )
		Receive Ports - FPGA RX interface Ports for gt0.
gt0_rxdisperr_out	out	std_logic_vector ( 3 downto 0 )
		Receive Ports - RX 8B/10B Decoder Ports for gt0.
gt0_rxnotintable_out	out	std_logic_vector ( 3 downto 0 )
gt0_rxbyteisaligned_out	out	std_logic
		Receive Ports - RX Byte and Word Alignment Ports for gt0.
gt0_rxbyterealign_out	out	std_logic
gt0_rxcommadet_out	out	std_logic
gt0_rxchariscomma_out	out	std_logic_vector ( 3 downto 0 )
		Receive Ports - RX8B/10B Decoder Ports for gt0.
gt0_rxcharisk_out	out	std_logic_vector ( 3 downto 0 )
gt0_rxresetdone_out	out	std_logic
		Receive Ports -RX Initialization and Reset Ports for gt0.
gt0_txdata_in	in	std_logic_vector ( 31 downto 0 )
		Transmit Ports - TX Data Path interface gt0.
gt0_txresetdone_out	out	std_logic
		Transmit Ports - TX Initialization and Reset Ports for gt0.
gt0_txcharisk_in	in	std_logic_vector ( 3 downto 0 )
		Transmit Transmit Ports - 8b10b Encoder Control Ports gt0.
gt0_txbufstatus_out	out	std_logic_vector ( 1 downto 0 )
		Transmit Ports - TX Buffer Ports for gt0.
gt1_loopback_in	in	std_logic_vector ( 2 downto 0 )
		Loopback Ports for gt1.
gt1_rxpd_in	in	std_logic_vector ( 1 downto 0 )
		Power-Down Ports for gt1.
gt1_txpd_in	in	std_logic_vector ( 1 downto 0 )
gt1_rxdata_out	out	std_logic_vector ( 31 downto 0 )
		Receive Ports - FPGA RX interface Ports for gt1.
gt1_rxdisperr_out	out	std_logic_vector ( 3 downto 0 )
		Receive Ports - RX 8B/10B Decoder Ports for gt1.
gt1_rxnotintable_out	out	std_logic_vector ( 3 downto 0 )
gt1_rxbyteisaligned_out	out	std_logic
		Receive Ports - RX Byte and Word Alignment Ports for gt1.
gt1_rxbyterealign_out	out	std_logic
gt1_rxcommadet_out	out	std_logic
gt1_rxchariscomma_out	out	std_logic_vector ( 3 downto 0 )
		Receive Ports - RX8B/10B Decoder Ports for gt1.
gt1_rxcharisk_out	out	std_logic_vector ( 3 downto 0 )
gt1_rxresetdone_out	out	std_logic
		Receive Ports -RX Initialization and Reset Ports for gt1.
gt1_txdata_in	in	std_logic_vector ( 31 downto 0 )
		Transmit Ports - TX Data Path interface gt1.
gt1_txresetdone_out	out	std_logic
		Transmit Ports - TX Initialization and Reset Ports for gt1.
gt1_txcharisk_in	in	std_logic_vector ( 3 downto 0 )
		Transmit Transmit Ports - 8b10b Encoder Control Ports for gt1.
gt1_txbufstatus_out	out	std_logic_vector ( 1 downto 0 )
		Transmit Ports - TX Buffer Ports for gt1.
gt2_loopback_in	in	std_logic_vector ( 2 downto 0 )
		Loopback Ports for gt2.
gt2_rxpd_in	in	std_logic_vector ( 1 downto 0 )
		Power-Down Ports for gt2.
gt2_txpd_in	in	std_logic_vector ( 1 downto 0 )
gt2_rxdata_out	out	std_logic_vector ( 31 downto 0 )
		Receive Ports - FPGA RX interface Ports for gt2.
gt2_rxdisperr_out	out	std_logic_vector ( 3 downto 0 )
		Receive Ports - RX 8B/10B Decoder Ports for gt2.
gt2_rxnotintable_out	out	std_logic_vector ( 3 downto 0 )
gt2_rxbyteisaligned_out	out	std_logic
		Receive Ports - RX Byte and Word Alignment Ports for gt2.
gt2_rxbyterealign_out	out	std_logic
gt2_rxcommadet_out	out	std_logic
gt2_rxchariscomma_out	out	std_logic_vector ( 3 downto 0 )
		Receive Ports - RX8B/10B Decoder Ports for gt2.
gt2_rxcharisk_out	out	std_logic_vector ( 3 downto 0 )
gt2_rxresetdone_out	out	std_logic
		Receive Ports -RX Initialization and Reset Ports for gt2.
gt2_txdata_in	in	std_logic_vector ( 31 downto 0 )
		Transmit Ports - TX Data Path interface for gt2.
gt2_txresetdone_out	out	std_logic
		Transmit Ports - TX Fabric Clock Output Control Ports for gt2.
gt2_txcharisk_in	in	std_logic_vector ( 3 downto 0 )
		Transmit Transmit Ports - 8b10b Encoder Control Ports for gt2.
gt2_txbufstatus_out	out	std_logic_vector ( 1 downto 0 )
		Transmit Ports - TX Buffer Ports for gt2.
gt3_loopback_in	in	std_logic_vector ( 2 downto 0 )
		Loopback Ports for gt3.
gt3_rxpd_in	in	std_logic_vector ( 1 downto 0 )
		Power-Down Ports for gt3.
gt3_txpd_in	in	std_logic_vector ( 1 downto 0 )
gt3_rxdata_out	out	std_logic_vector ( 31 downto 0 )
		Receive Ports - FPGA RX interface Ports for gt3.
gt3_rxdisperr_out	out	std_logic_vector ( 3 downto 0 )
		Receive Ports - RX 8B/10B Decoder Ports for gt3.
gt3_rxnotintable_out	out	std_logic_vector ( 3 downto 0 )
gt3_rxbyteisaligned_out	out	std_logic
		Receive Ports - RX Byte and Word Alignment Ports for gt3.
gt3_rxbyterealign_out	out	std_logic
gt3_rxcommadet_out	out	std_logic
gt3_rxchariscomma_out	out	std_logic_vector ( 3 downto 0 )
		Receive Ports - RX8B/10B Decoder Ports for gt3.
gt3_rxcharisk_out	out	std_logic_vector ( 3 downto 0 )
gt3_rxresetdone_out	out	std_logic
		Receive Ports -RX Initialization and Reset Ports for gt3.
gt3_txdata_in	in	std_logic_vector ( 31 downto 0 )
		Transmit Ports - TX Data Path interface for gt3.
gt3_txresetdone_out	out	std_logic
		Transmit Ports - TX Initialization and Reset Ports for gt3.
gt3_txcharisk_in	in	std_logic_vector ( 3 downto 0 )
		Transmit Transmit Ports - 8b10b Encoder Control Ports for gt3.
gt3_txbufstatus_out	out	std_logic_vector ( 1 downto 0 )
		Transmit Ports - TX Buffer Ports for gt3.
GT0_QPLLLOCK_OUT	out	std_logic
		COMMON PORTS.
GT0_QPLLREFCLKLOST_OUT	out	std_logic
sysclk_in	in	std_logic

Detailed Description

Quad MGT wrapper.

It creates top MGT wrapper for Quad with TX and RX 11.2Gbps, Ref clk = 280MHz it only creates ports that are used in the MGT generation vhdl

Author

Mohammed Siyad

Definition at line 16 of file min_latency_1quad_11g2_RxTX_wrapper.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1quad_11g2_RxTX_wrapper.vhd