RTL Architecture Reference

Quad MGT wrapper. More...

Signals
tied_to_ground_i	std_logic
tied_to_ground_vec_i	std_logic_vector ( 63 downto 0 )
tied_to_vcc_i	std_logic
tied_to_vcc_vec_i	std_logic_vector ( 7 downto 0 )

Attributes
DowngradeIPIdentifiedWarnings	string
DowngradeIPIdentifiedWarnings	architecture is " yes "
CORE_GENERATION_INFO	string
CORE_GENERATION_INFO	architecture is " min_latency_1_quad_rx_tx , gtwizard_v3_6_5 , {protocol_file = Start_from_scratch} "

Instantiations
min_latency_1_quad_rx_tx_support_i	min_latency_1_quad_rx_tx_support <Entity min_latency_1_quad_rx_tx_support>

Detailed Description

Quad MGT wrapper.

It creates top MGT wrapper for Quad with TX and RX 11.2Gbps, Ref clk = 280MHz it only creates ports that are used in the MGT generation vhdl

Author

Mohammed Siyad

Definition at line 212 of file min_latency_1quad_11g2_RxTX_wrapper.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/MGT/vhdl/min_latency_1quad_11g2_RxTX_wrapper.vhd