 |
eFEX firmware
1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards
|
Back to eFEX documentation
|
eFEX firmware
1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards
|
MGT ipbus control. More...
Entities | |
| Behavioral | architecture |
| MGT ipbus control. More... | |
Libraries | |
| IEEE | |
| work | |
| ipbus_lib | |
Use Clauses | |
| STD_LOGIC_1164 | |
| numeric_std | |
| ipbus | |
| ipbus_decode_efex_mgt_top | Package <ipbus_decode_efex_mgt_top> |
Generics | |
| MGT_QUAD_ENABLE | std_logic_vector ( 19 downto 0 ) := x " 00000 " |
| enable the quad in the design | |
| MGT_USE_OTHER_CLK | std_logic_vector ( 19 downto 0 ) := x " 00000 " |
| tx or rx clock selection | |
| MGT_TX_POWER | std_logic_vector ( 79 downto 0 ) := ( others = > ' 0 ' ) |
| power down to tx | |
| MGT_RX_POWER | std_logic_vector ( 79 downto 0 ) := ( others = > ' 0 ' ) |
| power down to rx | |
Ports | ||
| clk280_tx | in | std_logic_vector ( 79 downto 0 ) |
| tx clock of the all the mgts | ||
| clk280_rx | in | std_logic_vector ( 79 downto 0 ) |
| rx clock of the all the mgts | ||
| clk280 | in | std_logic |
| fabric clock of clk280MHz | ||
| clk40 | in | std_logic |
| fabric clock of 40MHz | ||
| BCR_in | in | std_logic |
| BCR from TTC information. | ||
| ipb_clk | in | std_logic |
| ipbus clock | ||
| ipb_rst | in | std_logic |
| ipbus reset | ||
| ipb_in | in | ipb_wbus |
| IPBus input bus going from master to slaves. | ||
| ipb_out | out | ipb_rbus |
| IPBus output bus going from slaves to master. | ||
| loopback | out | std_logic_vector ( 59 downto 0 ) |
| loopback setting for all the MGTs | ||
| softreset_tx | out | std_logic_vector ( 19 downto 0 ) |
| softreset_tx for all the Quads | ||
| softreset_rx | out | std_logic_vector ( 19 downto 0 ) |
| softreset_rx for all the Quads | ||
| mgt_enable | out | std_logic_vector ( 79 downto 0 ) |
| mgt enable for the MGTs | ||
| qpll_lock | in | std_logic_vector ( 19 downto 0 ) |
| qpllock for the quads | ||
| qpll_refclklost | in | std_logic_vector ( 19 downto 0 ) |
| qpll_refclklost for the quads | ||
| phase_mux | out | std_logic_vector ( 319 downto 0 ) |
| phase_mux | ||
| bc_cntr_0 | in | std_logic_vector ( 139 downto 0 ) |
| bc cntr for all the gt0 of the MGTs | ||
| bc_cntr_1 | in | std_logic_vector ( 139 downto 0 ) |
| bc cntr for all the gt1 of the MGTs | ||
| bc_cntr_2 | in | std_logic_vector ( 139 downto 0 ) |
| bc cntr for all the gt2 of the MGTs | ||
| bc_cntr_3 | in | std_logic_vector ( 139 downto 0 ) |
| bc cntr for all the gt3 of the MGTs | ||
| bc_mux_cntr_0 | in | std_logic_vector ( 139 downto 0 ) |
| bc_mux_cntr_0 for gt0 of the MGTs | ||
| bc_mux_cntr_1 | in | std_logic_vector ( 139 downto 0 ) |
| bc_mux_cntr_1 for gt1 of the MGTs | ||
| bc_mux_cntr_2 | in | std_logic_vector ( 139 downto 0 ) |
| bc_mux_cntr_2 for gt2 of the MGTs | ||
| bc_mux_cntr_3 | in | std_logic_vector ( 139 downto 0 ) |
| bc_mux_cntr_3 for gt3 of the MGTs | ||
| delay_cntr | in | std_logic_vector ( 319 downto 0 ) |
| first stage delay counters | ||
| BC_Reg_sel | out | std_logic_vector ( 319 downto 0 ) |
| mux setting for BC mux | ||
| mux_sel | out | std_logic_vector ( 319 downto 0 ) |
| mux setting for the first stage mux | ||
| rx_resetdone | in | std_logic_vector ( 79 downto 0 ) |
| rx resetdone for all MGTs | ||
| rx_fsm_resetdone | in | std_logic_vector ( 79 downto 0 ) |
| rx_fsm_resetdone for all MGTs | ||
| rx_byteisaligned | in | std_logic_vector ( 79 downto 0 ) |
| rx_byteisaligned for all MGTs | ||
| crc_error_chan | in | std_logic_vector ( 79 downto 0 ) |
| crc errors for all MGTs | ||
| tx_resetdone | in | std_logic_vector ( 79 downto 0 ) |
| tx resetdone for all MGTs | ||
| tx_fsm_resetdone | in | std_logic_vector ( 79 downto 0 ) |
| tx_fsm_resetdone for all MGTs | ||
| tx_bufstatus | in | std_logic_vector ( 159 downto 0 ) |
| tx_bufstatus for all MGTs | ||
| rx_realign | in | std_logic_vector ( 79 downto 0 ) |
| rx_realign for all MGTs | ||
| rx_disperr | in | std_logic_vector ( 319 downto 0 ) |
| rx_disperr for all MGTs | ||
| encode_error | in | std_logic_vector ( 319 downto 0 ) |
| encode_error for all MGTs | ||
| kchar_mgt | out | std_logic_vector ( 79 downto 0 ) |
| kchar_mgt all MGTs | ||
| rxdata_mgt0 | in | std_logic_vector ( 639 downto 0 ) |
| rx data from all gt0 in the all QAUDs | ||
| rxdata_mgt1 | in | std_logic_vector ( 639 downto 0 ) |
| rx data from all gt1 in the all QAUDs | ||
| rxdata_mgt2 | in | std_logic_vector ( 639 downto 0 ) |
| rx data from all gt2 in the all QAUDs | ||
| rxdata_mgt3 | in | std_logic_vector ( 639 downto 0 ) |
| rx data from all gt3 in the all QAUDs | ||
| ram_data_mgt0 | out | std_logic_vector ( 4559 downto 0 ) |
| ram data from all channel 0 in the all channels | ||
| ram_data_mgt1 | out | std_logic_vector ( 4559 downto 0 ) |
| ram_data_mgt2 | out | std_logic_vector ( 4559 downto 0 ) |
| ram data from all channel 2 in the all channels | ||
| ram_data_mgt3 | out | std_logic_vector ( 4559 downto 0 ) |
| disperr_error | out | std_logic_vector ( 79 downto 0 ) |
| disperr_error in all the MGTs | ||
| notable_error | out | std_logic_vector ( 79 downto 0 ) |
| d notable_error in all the MGTs | ||
MGT ipbus control.
This Module combines all the slaves of the MGTs in the design and connects to the ipbus registers. it uses generic values that allow to implement only the slaves of enabled quads in the design Implements the control and status interface to all of the MGTs in the design as follows:
Definition at line 34 of file mgt_slaves.vhd.
|
Library |
Definition at line 25 of file mgt_slaves.vhd.
1.9.1