official/Doc/mgt__slaves_8vhd_source.html

 library IEEE;

 use IEEE.STD_LOGIC_1164.all;

 use ieee.numeric_std.all;

 library work;

 library ipbus_lib;

 use ipbus_lib.ipbus.all;

 use work.ipbus_decode_efex_mgt_top.all;


 entity mgt_slaves is

   generic (

     MGT_QUAD_ENABLE   : std_logic_vector(19 downto 0) := x"00000";

     MGT_USE_OTHER_CLK : std_logic_vector(19 downto 0) := x"00000";

     MGT_TX_POWER      : std_logic_vector(79 downto 0) := (others => '0');

     MGT_RX_POWER      : std_logic_vector(79 downto 0) := (others => '0')

     );

   port (

     clk280_tx   : in  std_logic_vector(79 downto 0);

     clk280_rx   : in  std_logic_vector(79 downto 0);

      clk280     : in std_logic ;

     clk40    : in  std_logic;

     BCR_in   : in  std_logic;

     ipb_clk  : in  std_logic;

     ipb_rst  : in  std_logic;

     ipb_in   : in  ipb_wbus;

     ipb_out  : out ipb_rbus;

     loopback : out std_logic_vector(59 downto 0);  -- 3 bits per quad

     softreset_tx    : out std_logic_vector(19 downto 0);

     softreset_rx    : out std_logic_vector(19 downto 0);

     mgt_enable      : out std_logic_vector(79 downto 0);

     qpll_lock       : in  std_logic_vector(19 downto 0);

     qpll_refclklost : in  std_logic_vector(19 downto 0);

     phase_mux       : out std_logic_vector(319 downto 0);

     bc_cntr_0       : in  std_logic_vector(139 downto 0);

     bc_cntr_1       : in  std_logic_vector(139 downto 0);

     bc_cntr_2       : in  std_logic_vector(139 downto 0);

     bc_cntr_3       : in  std_logic_vector(139 downto 0);

     bc_mux_cntr_0   : in  std_logic_vector(139 downto 0);

     bc_mux_cntr_1   : in  std_logic_vector(139 downto 0);

     bc_mux_cntr_2   : in  std_logic_vector(139 downto 0);

     bc_mux_cntr_3   : in  std_logic_vector(139 downto 0);


     --gt  channel

     delay_cntr       : in  std_logic_vector (319 downto 0);

     BC_Reg_sel       : out std_logic_vector (319 downto 0);

     mux_sel          : out std_logic_vector (319 downto 0);

     rx_resetdone     : in  std_logic_vector (79 downto 0);

     rx_fsm_resetdone : in  std_logic_vector (79 downto 0);

     rx_byteisaligned : in  std_logic_vector (79 downto 0);

     crc_error_chan   : in  std_logic_vector (79 downto 0);

     tx_resetdone     : in  std_logic_vector (79 downto 0);

     tx_fsm_resetdone : in  std_logic_vector (79 downto 0);

     tx_bufstatus     : in  std_logic_vector (159 downto 0);

     rx_realign       : in  std_logic_vector (79 downto 0);

     rx_disperr       : in  std_logic_vector (319 downto 0);

     encode_error     : in  std_logic_vector (319 downto 0);

     kchar_mgt         : out std_logic_vector (79 downto 0);

     rxdata_mgt0       : in  std_logic_vector (639 downto 0);

     rxdata_mgt1       : in  std_logic_vector (639 downto 0);

     rxdata_mgt2       : in  std_logic_vector (639 downto 0);

     rxdata_mgt3       : in  std_logic_vector (639 downto 0);

     ram_data_mgt0     : out std_logic_vector (4559 downto 0);

     ---! ram data from all channel 1 in the all channels

     ram_data_mgt1     : out std_logic_vector (4559 downto 0);

     ram_data_mgt2     : out std_logic_vector (4559 downto 0);

     ---! ram data from all channel 3 in the all channels

     ram_data_mgt3     : out std_logic_vector (4559 downto 0);

     disperr_error     : out std_logic_vector (79 downto 0);

     notable_error     : out std_logic_vector (79 downto 0)


     );


 end mgt_slaves;


 architecture Behavioral of mgt_slaves is


 --constant NSLV: positive := 16;

   signal ipbw         : ipb_wbus_array(N_SLAVES-1 downto 0);

   signal ipbr, ipbr_d : ipb_rbus_array(N_SLAVES-1 downto 0);

   signal clock        : std_logic_vector(79 downto 0);


   -- ipbus number assignment, here we link the constants defined in the IPbus address map with the array used in the for generate

   -- we should try and keep this the same for every FPGA, but if that it not possible we can define it in a different file and

   -- make it FPGA dependent


   type MGT_IPBUS_NUMBER is array(19 downto 0) of integer;

   constant mgt_n : MGT_IPBUS_NUMBER := (N_SLV_MGT_219, N_SLV_MGT_218, N_SLV_MGT_217, N_SLV_MGT_216, N_SLV_MGT_215,

                                         N_SLV_MGT_214, N_SLV_MGT_213, N_SLV_MGT_212, N_SLV_MGT_211, N_SLV_MGT_210,

                                         N_SLV_MGT_119, N_SLV_MGT_118, N_SLV_MGT_117, N_SLV_MGT_116, N_SLV_MGT_115,

                                         N_SLV_MGT_114, N_SLV_MGT_113, N_SLV_MGT_112, N_SLV_MGT_111, N_SLV_MGT_110);


 begin


   mgt_fabric : entity ipbus_lib.ipbus_fabric_sel

     generic map(NSLV      => N_SLAVES,  --defined in ipbus_decode_mgt_slvs

                 SEL_WIDTH => ipbus_sel_width)

     port map(

       ipb_in          => ipb_in,

       ipb_out         => ipb_out,

       sel             => ipbus_sel_efex_mgt_top(ipb_in.ipb_addr),

       ipb_to_slaves   => ipbw,

       ipb_from_slaves => ipbr

       );


   QUAD_FOR : for i in 0 to 19 generate


     -- Use rx clock in case the MGT is using the other clock and so it is transmitter only

     -- Maybe this should be done using the rx power instead as the new board will not have any slow MGT

     clock(i*4+3 downto i*4) <= Clk280_rx(i*4+3 downto i*4) when MGT_USE_OTHER_CLK(i) = '0' else

                                Clk280_tx(i*4+3 downto i*4);


     quad : entity work.mgt_quad_slaves

       generic map(ENABLE => MGT_QUAD_ENABLE(i)

                   )

       port map (

         rxclk280         => clock(i*4+3 downto i*4),

         clk280           => clk280,

         clk40            => clk40,

         BCR_in           => BCR_in,

         ipb_clk          => ipb_clk,

         ipb_rst          => ipb_rst,

         ipb_in           => ipbw(mgt_n(i)),

         ipb_out          => ipbr(mgt_n(i)),

         tx_pd            => MGT_TX_POWER(i*4+3 downto i*4),      --79

         rx_pd            => MGT_RX_POWER(i*4+3 downto i*4),      --79

         loopback         => loopback(i*3+2 downto i*3),          --59

        -- error_counter    => error_counter(i*64+63 downto i*64),  --1279

         bc_reg_sel       => bc_reg_sel(i*16+15 downto i*16),     --319

         mux_sel          => mux_sel(i*16+15 downto i*16),        --319

         bc_cntr_0        => bc_cntr_0(i*7+6 downto i*7),         --99

         bc_cntr_1        => bc_cntr_1(i*7+6 downto i*7),         --99

         bc_cntr_2        => bc_cntr_2(i*7+6 downto i*7),         --99

         bc_cntr_3        => bc_cntr_3(i*7+6 downto i*7),         --99

         bc_mux_cntr_0    => bc_mux_cntr_0(i*7+6 downto i*7),     --99

         bc_mux_cntr_1    => bc_mux_cntr_1(i*7+6 downto i*7),     --99

         bc_mux_cntr_2    => bc_mux_cntr_2(i*7+6 downto i*7),     --99

         bc_mux_cntr_3    => bc_mux_cntr_3(i*7+6 downto i*7),     --99

         delay_cntr_0     => delay_cntr(i*16+3 downto i*16+0),    --319

         delay_cntr_1     => delay_cntr(i*16+7 downto i*16+4),    --319

         delay_cntr_2     => delay_cntr(i*16+11 downto i*16+8),   --319

         delay_cntr_3     => delay_cntr(i*16+15 downto i*16+12),  --319

         softreset_tx     => softreset_tx(i),                     --19

         softreset_rx     => softreset_rx(i),                     --19

         mgt_enable       => mgt_enable (i*4+3 downto i*4),       --79

         phase_mux        => phase_mux(i*16+15 downto i*16),      --319

         qpll_lock        => qpll_lock(i),                        --19

         qpll_refclklost  => qpll_refclklost(i),                  --19

         rx_resetdone     => rx_resetdone(i*4+3 downto i*4),      --79

         rx_fsm_resetdone => rx_fsm_resetdone(i*4+3 downto i*4),  --79

         rx_byteisaligned => rx_byteisaligned(i*4+3 downto i*4),  --79

         tx_resetdone     => tx_resetdone(i*4+3 downto i*4),      --79

         tx_fsm_resetdone => tx_fsm_resetdone(i*4+3 downto i*4),  --79

         tx_bufstatus     => tx_bufstatus(i*8+7 downto i*8),

         rx_realign       => rx_realign(i*4+3 downto i*4),        --79

         crc_error        => crc_error_chan(i*4+3 downto i*4),    --79

         rx_disperr       => rx_disperr(i*16+15 downto i*16),     --319

         encode_error     => encode_error(i*16+15 downto i*16),   --319

         rxdata_gt0       => rxdata_mgt0 (i*32+31 downto i*32),   --639

         rxdata_gt1       => rxdata_mgt1 (i*32+31 downto i*32),   --639

         rxdata_gt2       => rxdata_mgt2 (i*32+31 downto i*32),   --639

         rxdata_gt3       => rxdata_mgt3 (i*32+31 downto i*32),   --639


         ram_data_gt0     => ram_data_mgt0(i*228+227 downto i*228),  --639

         ram_data_gt1     => ram_data_mgt1(i*228+227 downto i*228),  --639

         ram_data_gt2     => ram_data_mgt2(i*228+227 downto i*228),  --639

         ram_data_gt3     => ram_data_mgt3(i*228+227 downto i*228),  --639


         disperr_error    => disperr_error (i*4+3 downto i*4),

         notable_error    => notable_error (i*4+3 downto i*4)

         );

   end generate;


 end Behavioral;

ipbus_decode_efex_mgt_top
Definition: ipbus_decode_efex_mgt_top.vhd:14

mgt_quad_slaves
MGT quad ipbus control.
Definition: mgt_quad_slaves.vhd:18

mgt_quad_slaves.delay_cntr_2
in delay_cntr_2 std_logic_vector( 3 downto  0)
first stage delay count of gt2
Definition: mgt_quad_slaves.vhd:79

mgt_quad_slaves.qpll_lock
in qpll_lock std_logic
qpll lock of the MGT if high
Definition: mgt_quad_slaves.vhd:49

mgt_quad_slaves.mgt_enable
out mgt_enable std_logic_vector( 3 downto  0)
mgt enable of the quad
Definition: mgt_quad_slaves.vhd:85

mgt_quad_slaves.softreset_rx
out softreset_rx std_logic
rx soft reset of the quad
Definition: mgt_quad_slaves.vhd:47

mgt_quad_slaves.clk40
in clk40 std_logic
fabric clock of 40MHz
Definition: mgt_quad_slaves.vhd:27

mgt_quad_slaves.bc_cntr_1
in bc_cntr_1 std_logic_vector( 6 downto  0)
bc value of gt1
Definition: mgt_quad_slaves.vhd:61

mgt_quad_slaves.ipb_rst
in ipb_rst std_logic
ipbus reset
Definition: mgt_quad_slaves.vhd:33

mgt_quad_slaves.ram_data_gt0
out ram_data_gt0 std_logic_vector( 227 downto  0)
ram_data from the plyback ram gt0
Definition: mgt_quad_slaves.vhd:114

mgt_quad_slaves.BCR_in
in BCR_in std_logic
BCR from TTC information.
Definition: mgt_quad_slaves.vhd:29

mgt_quad_slaves.delay_cntr_1
in delay_cntr_1 std_logic_vector( 3 downto  0)
first stage delay count of gt1
Definition: mgt_quad_slaves.vhd:77

mgt_quad_slaves.rx_pd
in rx_pd std_logic_vector( 3 downto  0)
power control for rx side of the mgt
Definition: mgt_quad_slaves.vhd:55

mgt_quad_slaves.tx_resetdone
in tx_resetdone std_logic_vector( 3 downto  0)
tx reset done of the quad if high is done
Definition: mgt_quad_slaves.vhd:94

mgt_quad_slaves.rx_realign
in rx_realign std_logic_vector( 3 downto  0)
rx realign status
Definition: mgt_quad_slaves.vhd:100

mgt_quad_slaves.bc_reg_sel
out bc_reg_sel std_logic_vector( 15 downto  0)
BC level mux setting value.
Definition: mgt_quad_slaves.vhd:41

mgt_quad_slaves.crc_error
in crc_error std_logic_vector( 3 downto  0)
crc error of the quad
Definition: mgt_quad_slaves.vhd:83

mgt_quad_slaves.tx_pd
in tx_pd std_logic_vector( 3 downto  0)
power control for tx side of the mgt
Definition: mgt_quad_slaves.vhd:53

mgt_quad_slaves.bc_mux_cntr_3
in bc_mux_cntr_3 std_logic_vector( 6 downto  0)
bc value after the mux gt3
Definition: mgt_quad_slaves.vhd:73

mgt_quad_slaves.loopback
out loopback std_logic_vector( 2 downto  0)
Loopback Ports.
Definition: mgt_quad_slaves.vhd:39

mgt_quad_slaves.ram_data_gt2
out ram_data_gt2 std_logic_vector( 227 downto  0)
ram_data from the plyback ram gt2
Definition: mgt_quad_slaves.vhd:118

mgt_quad_slaves.rxclk280
in rxclk280 std_logic_vector( 3 downto  0)
rxclk
Definition: mgt_quad_slaves.vhd:25

mgt_quad_slaves.bc_cntr_0
in bc_cntr_0 std_logic_vector( 6 downto  0)
bc value of gt0
Definition: mgt_quad_slaves.vhd:59

mgt_quad_slaves.bc_mux_cntr_1
in bc_mux_cntr_1 std_logic_vector( 6 downto  0)
bc value after the mux gt1
Definition: mgt_quad_slaves.vhd:69

mgt_quad_slaves.mux_sel
out mux_sel std_logic_vector( 15 downto  0)
first stage sync mux setting value
Definition: mgt_quad_slaves.vhd:43

mgt_quad_slaves.tx_bufstatus
in tx_bufstatus std_logic_vector( 7 downto  0)
tx buffer status
Definition: mgt_quad_slaves.vhd:98

mgt_quad_slaves.delay_cntr_3
in delay_cntr_3 std_logic_vector( 3 downto  0)
first stage delay count of gt3
Definition: mgt_quad_slaves.vhd:81

mgt_quad_slaves.ram_data_gt3
out ram_data_gt3 std_logic_vector( 227 downto  0)
ram_data from the plyback ram gt3
Definition: mgt_quad_slaves.vhd:120

mgt_quad_slaves.rx_resetdone
in rx_resetdone std_logic_vector( 3 downto  0)
rx reset done of the quad if high is done
Definition: mgt_quad_slaves.vhd:88

mgt_quad_slaves.tx_fsm_resetdone
in tx_fsm_resetdone std_logic_vector( 3 downto  0)
tx fsm reset done of the quad if high is done
Definition: mgt_quad_slaves.vhd:96

mgt_quad_slaves.rx_byteisaligned
in rx_byteisaligned std_logic_vector( 3 downto  0)
RX Byte and Word Alignment.
Definition: mgt_quad_slaves.vhd:92

mgt_quad_slaves.delay_cntr_0
in delay_cntr_0 std_logic_vector( 3 downto  0)
first stage delay count of gt0
Definition: mgt_quad_slaves.vhd:75

mgt_quad_slaves.notable_error
out notable_error std_logic_vector( 3 downto  0)
notable_error
Definition: mgt_quad_slaves.vhd:127

mgt_quad_slaves.clk280
in clk280 std_logic
fabric clock 280MHz
Definition: mgt_quad_slaves.vhd:23

mgt_quad_slaves.rx_disperr
in rx_disperr std_logic_vector( 15 downto  0)
rx disperr error
Definition: mgt_quad_slaves.vhd:102

mgt_quad_slaves.ipb_clk
in ipb_clk std_logic
ipbus clock
Definition: mgt_quad_slaves.vhd:31

mgt_quad_slaves.bc_cntr_2
in bc_cntr_2 std_logic_vector( 6 downto  0)
bc value of gt2
Definition: mgt_quad_slaves.vhd:63

mgt_quad_slaves.rxdata_gt3
in rxdata_gt3 std_logic_vector( 31 downto  0)
rx_data from gt3
Definition: mgt_quad_slaves.vhd:112

mgt_quad_slaves.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: mgt_quad_slaves.vhd:37

mgt_quad_slaves.rx_fsm_resetdone
in rx_fsm_resetdone std_logic_vector( 3 downto  0)
rx fsm reset done of the quad if high is done
Definition: mgt_quad_slaves.vhd:90

mgt_quad_slaves.bc_cntr_3
in bc_cntr_3 std_logic_vector( 6 downto  0)
bc value of gt3
Definition: mgt_quad_slaves.vhd:65

mgt_quad_slaves.disperr_error
out disperr_error std_logic_vector( 3 downto  0)
disperr_error
Definition: mgt_quad_slaves.vhd:122

mgt_quad_slaves.bc_mux_cntr_0
in bc_mux_cntr_0 std_logic_vector( 6 downto  0)
bc value after the mux gt0
Definition: mgt_quad_slaves.vhd:67

mgt_quad_slaves.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: mgt_quad_slaves.vhd:35

mgt_quad_slaves.rxdata_gt0
in rxdata_gt0 std_logic_vector( 31 downto  0)
rx_data from gt0
Definition: mgt_quad_slaves.vhd:106

mgt_quad_slaves.encode_error
in encode_error std_logic_vector( 15 downto  0)
B/10B Decoder error.
Definition: mgt_quad_slaves.vhd:104

mgt_quad_slaves.bc_mux_cntr_2
in bc_mux_cntr_2 std_logic_vector( 6 downto  0)
bc value after the mux gt2
Definition: mgt_quad_slaves.vhd:71

mgt_quad_slaves.qpll_refclklost
in qpll_refclklost std_logic
qpll refrence clcok lost if high
Definition: mgt_quad_slaves.vhd:51

mgt_quad_slaves.rxdata_gt2
in rxdata_gt2 std_logic_vector( 31 downto  0)
rx_data from gt2
Definition: mgt_quad_slaves.vhd:110

mgt_quad_slaves.softreset_tx
out softreset_tx std_logic
tx soft reset of the quad
Definition: mgt_quad_slaves.vhd:45

mgt_quad_slaves.ram_data_gt1
out ram_data_gt1 std_logic_vector( 227 downto  0)
ram_data from the plyback ram gt1
Definition: mgt_quad_slaves.vhd:116

mgt_quad_slaves.rxdata_gt1
in rxdata_gt1 std_logic_vector( 31 downto  0)
rx_data from gt1
Definition: mgt_quad_slaves.vhd:108

mgt_slaves.Behavioral
MGT ipbus control.
Definition: mgt_slaves.vhd:150

mgt_slaves
MGT ipbus control.
Definition: mgt_slaves.vhd:34

mgt_slaves.ram_data_mgt0
out ram_data_mgt0 std_logic_vector( 4559 downto  0)
ram data from all channel 0 in the all channels
Definition: mgt_slaves.vhd:133

mgt_slaves.delay_cntr
in delay_cntr std_logic_vector( 319 downto  0)
first stage delay counters
Definition: mgt_slaves.vhd:97

mgt_slaves.kchar_mgt
out kchar_mgt std_logic_vector( 79 downto  0)
kchar_mgt all MGTs
Definition: mgt_slaves.vhd:123

mgt_slaves.rx_fsm_resetdone
in rx_fsm_resetdone std_logic_vector( 79 downto  0)
rx_fsm_resetdone for all MGTs
Definition: mgt_slaves.vhd:105

mgt_slaves.bc_mux_cntr_2
in bc_mux_cntr_2 std_logic_vector( 139 downto  0)
bc_mux_cntr_2 for gt2 of the MGTs
Definition: mgt_slaves.vhd:91

mgt_slaves.clk40
in clk40 std_logic
fabric clock of 40MHz
Definition: mgt_slaves.vhd:53

mgt_slaves.ipb_rst
in ipb_rst std_logic
ipbus reset
Definition: mgt_slaves.vhd:59

mgt_slaves.rxdata_mgt1
in rxdata_mgt1 std_logic_vector( 639 downto  0)
rx data from all gt1 in the all QAUDs
Definition: mgt_slaves.vhd:127

mgt_slaves.BCR_in
in BCR_in std_logic
BCR from TTC information.
Definition: mgt_slaves.vhd:55

mgt_slaves.tx_fsm_resetdone
in tx_fsm_resetdone std_logic_vector( 79 downto  0)
tx_fsm_resetdone for all MGTs
Definition: mgt_slaves.vhd:113

mgt_slaves.qpll_refclklost
in qpll_refclklost std_logic_vector( 19 downto  0)
qpll_refclklost for the quads
Definition: mgt_slaves.vhd:75

mgt_slaves.crc_error_chan
in crc_error_chan std_logic_vector( 79 downto  0)
crc errors for all MGTs
Definition: mgt_slaves.vhd:109

mgt_slaves.rxdata_mgt0
in rxdata_mgt0 std_logic_vector( 639 downto  0)
rx data from all gt0 in the all QAUDs
Definition: mgt_slaves.vhd:125

mgt_slaves.qpll_lock
in qpll_lock std_logic_vector( 19 downto  0)
qpllock for the quads
Definition: mgt_slaves.vhd:73

mgt_slaves.rxdata_mgt3
in rxdata_mgt3 std_logic_vector( 639 downto  0)
rx data from all gt3 in the all QAUDs
Definition: mgt_slaves.vhd:131

mgt_slaves.clk280_rx
in clk280_rx std_logic_vector( 79 downto  0)
rx clock of the all the mgts
Definition: mgt_slaves.vhd:49

mgt_slaves.rx_realign
in rx_realign std_logic_vector( 79 downto  0)
rx_realign for all MGTs
Definition: mgt_slaves.vhd:117

mgt_slaves.bc_cntr_3
in bc_cntr_3 std_logic_vector( 139 downto  0)
bc cntr for all the gt3 of the MGTs
Definition: mgt_slaves.vhd:85

mgt_slaves.softreset_tx
out softreset_tx std_logic_vector( 19 downto  0)
softreset_tx for all the Quads
Definition: mgt_slaves.vhd:67

mgt_slaves.bc_cntr_0
in bc_cntr_0 std_logic_vector( 139 downto  0)
bc cntr for all the gt0 of the MGTs
Definition: mgt_slaves.vhd:79

mgt_slaves.ram_data_mgt2
out ram_data_mgt2 std_logic_vector( 4559 downto  0)
ram data from all channel 2 in the all channels
Definition: mgt_slaves.vhd:137

mgt_slaves.MGT_RX_POWER
MGT_RX_POWER std_logic_vector( 79 downto  0) :=( others => '0')
power down to rx
Definition: mgt_slaves.vhd:44

mgt_slaves.rxdata_mgt2
in rxdata_mgt2 std_logic_vector( 639 downto  0)
rx data from all gt2 in the all QAUDs
Definition: mgt_slaves.vhd:129

mgt_slaves.bc_cntr_1
in bc_cntr_1 std_logic_vector( 139 downto  0)
bc cntr for all the gt1 of the MGTs
Definition: mgt_slaves.vhd:81

mgt_slaves.bc_mux_cntr_1
in bc_mux_cntr_1 std_logic_vector( 139 downto  0)
bc_mux_cntr_1 for gt1 of the MGTs
Definition: mgt_slaves.vhd:89

mgt_slaves.loopback
out loopback std_logic_vector( 59 downto  0)
loopback setting for all the MGTs
Definition: mgt_slaves.vhd:65

mgt_slaves.rx_byteisaligned
in rx_byteisaligned std_logic_vector( 79 downto  0)
rx_byteisaligned for all MGTs
Definition: mgt_slaves.vhd:107

mgt_slaves.rx_resetdone
in rx_resetdone std_logic_vector( 79 downto  0)
rx resetdone for all MGTs
Definition: mgt_slaves.vhd:103

mgt_slaves.bc_cntr_2
in bc_cntr_2 std_logic_vector( 139 downto  0)
bc cntr for all the gt2 of the MGTs
Definition: mgt_slaves.vhd:83

mgt_slaves.disperr_error
out disperr_error std_logic_vector( 79 downto  0)
disperr_error in all the MGTs
Definition: mgt_slaves.vhd:141

mgt_slaves.mgt_enable
out mgt_enable std_logic_vector( 79 downto  0)
mgt enable for the MGTs
Definition: mgt_slaves.vhd:71

mgt_slaves.phase_mux
out phase_mux std_logic_vector( 319 downto  0)
phase_mux
Definition: mgt_slaves.vhd:77

mgt_slaves.tx_resetdone
in tx_resetdone std_logic_vector( 79 downto  0)
tx resetdone for all MGTs
Definition: mgt_slaves.vhd:111

mgt_slaves.tx_bufstatus
in tx_bufstatus std_logic_vector( 159 downto  0)
tx_bufstatus for all MGTs
Definition: mgt_slaves.vhd:115

mgt_slaves.clk280_tx
in clk280_tx std_logic_vector( 79 downto  0)
tx clock of the all the mgts
Definition: mgt_slaves.vhd:47

mgt_slaves.BC_Reg_sel
out BC_Reg_sel std_logic_vector( 319 downto  0)
mux setting for BC mux
Definition: mgt_slaves.vhd:99

mgt_slaves.clk280
in clk280 std_logic
fabric clock of clk280MHz
Definition: mgt_slaves.vhd:51

mgt_slaves.MGT_QUAD_ENABLE
MGT_QUAD_ENABLE std_logic_vector( 19 downto  0) := x"00000"
enable the quad in the design
Definition: mgt_slaves.vhd:37

mgt_slaves.ipb_clk
in ipb_clk std_logic
ipbus clock
Definition: mgt_slaves.vhd:57

mgt_slaves.bc_mux_cntr_0
in bc_mux_cntr_0 std_logic_vector( 139 downto  0)
bc_mux_cntr_0 for gt0 of the MGTs
Definition: mgt_slaves.vhd:87

mgt_slaves.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: mgt_slaves.vhd:63

mgt_slaves.mux_sel
out mux_sel std_logic_vector( 319 downto  0)
mux setting for the first stage mux
Definition: mgt_slaves.vhd:101

mgt_slaves.MGT_USE_OTHER_CLK
MGT_USE_OTHER_CLK std_logic_vector( 19 downto  0) := x"00000"
tx or rx clock selection
Definition: mgt_slaves.vhd:39

mgt_slaves.notable_error
out notable_error std_logic_vector( 79 downto  0)
d notable_error in all the MGTs
Definition: mgt_slaves.vhd:145

mgt_slaves.encode_error
in encode_error std_logic_vector( 319 downto  0)
encode_error for all MGTs
Definition: mgt_slaves.vhd:121

mgt_slaves.rx_disperr
in rx_disperr std_logic_vector( 319 downto  0)
rx_disperr for all MGTs
Definition: mgt_slaves.vhd:119

mgt_slaves.bc_mux_cntr_3
in bc_mux_cntr_3 std_logic_vector( 139 downto  0)
bc_mux_cntr_3 for gt3 of the MGTs
Definition: mgt_slaves.vhd:93

mgt_slaves.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: mgt_slaves.vhd:61

mgt_slaves.softreset_rx
out softreset_rx std_logic_vector( 19 downto  0)
softreset_rx for all the Quads
Definition: mgt_slaves.vhd:69

mgt_slaves.MGT_TX_POWER
MGT_TX_POWER std_logic_vector( 79 downto  0) :=( others => '0')
power down to tx
Definition: mgt_slaves.vhd:41