official/Doc/mgt__quad__slaves_8vhd_source.html

 library IEEE;

 use IEEE.STD_LOGIC_1164.all;

 use ieee.numeric_std.all;

 library ipbus_lib;

 use ipbus_lib.ipbus.all;

 use work.ipbus_decode_efex_mgt_quad.all;


 entity mgt_quad_slaves is

   generic(ENABLE : in std_logic := '1'

           );

   port (

     clk280           : in  std_logic;

     rxclk280         : in  std_logic_vector(3 downto 0);

     clk40            : in  std_logic;

     BCR_in           : in  std_logic;

     ipb_clk          : in  std_logic;

     ipb_rst          : in  std_logic;

     ipb_in           : in  ipb_wbus;

     ipb_out          : out ipb_rbus;

     loopback         : out std_logic_vector(2 downto 0);

     bc_reg_sel       : out std_logic_vector(15 downto 0);

     mux_sel          : out std_logic_vector(15 downto 0);

     softreset_tx     : out std_logic;

     softreset_rx     : out std_logic;

     qpll_lock        : in  std_logic;

     qpll_refclklost  : in  std_logic;

     tx_pd            : in  std_logic_vector(3 downto 0);

     rx_pd            : in  std_logic_vector(3 downto 0);


    -- error_counter    : in  std_logic_vector(63 downto 0);

     bc_cntr_0        : in  std_logic_vector(6 downto 0);

     bc_cntr_1        : in  std_logic_vector(6 downto 0);

     bc_cntr_2        : in  std_logic_vector(6 downto 0);

     bc_cntr_3        : in  std_logic_vector(6 downto 0);

     bc_mux_cntr_0    : in  std_logic_vector(6 downto 0);

     bc_mux_cntr_1    : in  std_logic_vector(6 downto 0);

     bc_mux_cntr_2    : in  std_logic_vector(6 downto 0);

     bc_mux_cntr_3    : in  std_logic_vector(6 downto 0);

     delay_cntr_0     : in  std_logic_vector (3 downto 0);

     delay_cntr_1     : in  std_logic_vector (3 downto 0);

     delay_cntr_2     : in  std_logic_vector (3 downto 0);

     delay_cntr_3     : in  std_logic_vector (3 downto 0);

     crc_error        : in  std_logic_vector (3 downto 0);

     mgt_enable       : out std_logic_vector(3 downto 0);

     phase_mux        : out std_logic_vector(15 downto 0);

     rx_resetdone     : in  std_logic_vector (3 downto 0);

     rx_fsm_resetdone : in  std_logic_vector (3 downto 0);

     rx_byteisaligned : in  std_logic_vector (3 downto 0);

     tx_resetdone     : in  std_logic_vector (3 downto 0);

     tx_fsm_resetdone : in  std_logic_vector (3 downto 0);

     tx_bufstatus     : in  std_logic_vector (7 downto 0);

     rx_realign       : in  std_logic_vector (3 downto 0);

     rx_disperr       : in  std_logic_vector (15 downto 0);

     encode_error     : in  std_logic_vector (15 downto 0);

     rxdata_gt0       : in  std_logic_vector(31 downto 0);

     rxdata_gt1       : in  std_logic_vector(31 downto 0);

     rxdata_gt2       : in  std_logic_vector(31 downto 0);

     rxdata_gt3       : in  std_logic_vector(31 downto 0);

     ram_data_gt0     : out std_logic_vector(227 downto 0);

     ram_data_gt1     : out std_logic_vector(227 downto 0);

     ram_data_gt2     : out std_logic_vector(227 downto 0);

     ram_data_gt3     : out std_logic_vector(227 downto 0);

     disperr_error    : out  std_logic_vector(3 downto 0);

     notable_error    : out  std_logic_vector(3 downto 0)


     );


 end mgt_quad_slaves;


 architecture Behavioral of mgt_quad_slaves is

 --constant N_SLAVES: positive := 5;

   signal ipbw                                                               : ipb_wbus_array(N_SLAVES-1 downto 0);

   signal ipbr, ipbr_d                                                       : ipb_rbus_array(N_SLAVES-1 downto 0);

   signal error_counter_reset                                                : std_logic;

   signal encode_error_int, rx_disperr_int,rdy, mgtdata_enable               : std_logic_vector (3 downto 0);

   signal softreset_rx_int, softreset_tx_int, error_counter_reset_int        : std_logic;

   signal control_reg, synch_reg, pulse_reg, quad_status, phase_reg          : std_logic_vector (31 downto 0);

   signal pulse_reset, softreset_rx_i, error_counter_reset_i, softreset_tx_i : std_logic;

   signal clr_pulse_reg, cntr_reset,sel_bcn_or_bc_cnt                                          : std_logic;


 --  ####### Mark signals  ########

  attribute keep       : string ;

  attribute max_fanout : integer;

  attribute keep of       softreset_tx_i : signal is "true" ;

  attribute max_fanout of softreset_tx_i : signal is 40;

  attribute keep of       softreset_rx_i : signal is "true" ;

  attribute max_fanout of softreset_rx_i : signal is 40;

  attribute keep of       error_counter_reset_i : signal is "true" ;

  attribute max_fanout of error_counter_reset_i : signal is 40;

 --   #######################################


 begin

 --- quad fabric decoder

   ENABLED_QUAD : if ENABLE = '1' generate

     fabric_quad : entity ipbus_lib.ipbus_fabric_sel

       generic map(NSLV      => N_SLAVES,

                   SEL_WIDTH => ipbus_sel_width)

       port map(

         ipb_in          => ipb_in,

         ipb_out         => ipb_out,

         sel             => ipbus_sel_efex_mgt_quad(ipb_in.ipb_addr),

         ipb_to_slaves   => ipbw,

         ipb_from_slaves => ipbr

         );

   end generate ENABLED_QUAD;


   DISABLED_QUAD : if ENABLE = '0' generate

     fabric_quad : entity ipbus_lib.ipbus_fabric_sel

       generic map(NSLV      => N_SLAVES,

                   SEL_WIDTH => ipbus_sel_width)

       port map(

         ipb_in          => IPB_WBUS_NULL,

         ipb_out         => open,

         sel             => (others => '0'),

         ipb_to_slaves   => open,

         ipb_from_slaves => (others => IPB_RBUS_NULL)

         );

     ipb_out <= (x"DEADBEEF", '1', '0');

   end generate DISABLED_QUAD;


   encode_error_int(0) <= encode_error(0) or encode_error(1) or encode_error(2) or encode_error(3);

   encode_error_int(1) <= encode_error(4) or encode_error(5) or encode_error(6) or encode_error(7);

   encode_error_int(2) <= encode_error(8) or encode_error(9) or encode_error(10) or encode_error(11);

   encode_error_int(3) <= encode_error(12) or encode_error(13) or encode_error(14) or encode_error(15);


   notable_error <= encode_error_int;


   disperr_error <= rx_disperr_int;


   rx_disperr_int(0) <= rx_disperr(0) or rx_disperr(1) or rx_disperr(2) or rx_disperr(3);

   rx_disperr_int(1) <= rx_disperr(4) or rx_disperr(5) or rx_disperr(6) or rx_disperr(7);

   rx_disperr_int(2) <= rx_disperr(8) or rx_disperr(9) or rx_disperr(10) or rx_disperr(11);

   rx_disperr_int(3) <= rx_disperr(12) or rx_disperr(13) or rx_disperr(14) or rx_disperr(15);


   loopback                <= control_reg(2 downto 0);                          --- loopback signal

   mgt_enable              <= control_reg(7 downto 4);                          -- mgt enable signals

   rdy                     <= control_reg( 11 downto 8);                        -- rdy for dual state machine

   mgtdata_enable          <= control_reg( 15 downto 12);                       -- enable the input ram for capturing the rxdata

   bc_reg_sel              <= synch_reg (15 downto 0);                          -- 2nd stage BC level MUX selector

   mux_sel                 <= synch_reg (31 downto 16);                         -- 1st stage fine tune MUX selector

   softreset_tx_int        <= pulse_reg(0);                                     -- tx reset pulse

   softreset_rx_int        <= pulse_reg(1);                                     -- rxreset pulse

   error_counter_reset_int <= pulse_reg(2);                                     -- error counter reset pulse

   quad_status             <= x"0000000" & "00" & qpll_refclklost & qpll_lock;  --- concatenating  the pll  status signals

   softreset_tx            <= softreset_tx_i;

   softreset_rx            <= softreset_rx_i;

   phase_mux               <= phase_reg(15 downto 0);


   softreset_rx_pulse : entity work.led_stretch  -- softresetrx pulse generator

     port map(

       input  => softreset_rx_int,

       clk    => ipb_clk, --clk280(0),

       output => softreset_rx_i

       );


   softreset_tx_pulse : entity work.led_stretch  -- softresettx pulse generator

     port map(

       input  => softreset_tx_int,

       clk    => ipb_clk, --clk280(0),

       output => softreset_tx_i

       );


   error_counter_reset_pulse : entity work.led_stretch  -- pulse generator

     port map(

       input  => error_counter_reset_int,

       clk    => ipb_clk, --clk280(0),

       output => error_counter_reset_i

       );


   cntr_reset    <= error_counter_reset_i or softreset_rx_i;  -- error counter will be reset when rx is reset

   pulse_reset   <= softreset_rx_i or error_counter_reset_i or softreset_tx_i;

   clr_pulse_reg <= ipb_rst or pulse_reset;                   -- reset the pulse register with ipb reset or when it generates one pulse


 MGT_QUAD_Control : entity ipbus_lib.ipbus_ctrlreg_v  --- control register

     generic map (

         N_CTRL => 1,  --number of control reg

         N_STAT => 0)  --number of status reg

     port map(

       clk       => ipb_clk,

       reset     => ipb_rst,

       ipbus_in  => ipbw(N_SLV_QUAD_MGT_CONTROL),

       ipbus_out => ipbr(N_SLV_QUAD_MGT_CONTROL),

       d         => (others => (others => '0')) ,

       q(0)      => control_reg,

       stb       => open);


 MGT_QUAD_Synch: entity ipbus_lib.ipbus_ctrlreg_v -- reads the module ID register

     generic map (

         N_CTRL => 1,  --number of control reg

         N_STAT => 0)  --number of status reg

     port map(

       clk       => ipb_clk,

       reset     => ipb_rst,

       ipbus_in  => ipbw(N_SLV_QUAD_SYNCH_CONTROL),

       ipbus_out => ipbr(N_SLV_QUAD_SYNCH_CONTROL),

       d         => (others => (others => '0')) ,

       q(0)      => synch_reg,

       stb       => open);


 MGT_QUAD_Pulse: entity ipbus_lib.ipbus_ctrlreg_v -- reads the module ID register

     generic map (

         N_CTRL => 1,  --number of control reg

         N_STAT => 0)  --number of status reg

     port map(

       clk       => ipb_clk,

       reset     => clr_pulse_reg,

       ipbus_in  => ipbw(N_SLV_QUAD_MGT_PULSE),

       ipbus_out => ipbr(N_SLV_QUAD_MGT_PULSE),

       d         => (others => (others => '0')) ,

       q(0)      => pulse_reg,

       stb       => open);


 MGT_QUAD_status: entity ipbus_lib.ipbus_ctrlreg_v

     generic map (

         N_CTRL => 0,  --number of control reg

         N_STAT => 1)  --number of status reg

     port map(

       clk       => ipb_clk,

       reset     => ipb_rst,

       ipbus_in  => ipbw(N_SLV_QUAD_MGT_STATUS),

       ipbus_out => ipbr(N_SLV_QUAD_MGT_STATUS),

       d         => (0 => quad_status) ,

       q         => open,

       stb       => open);


 MGT_QUAD_PHASE: entity ipbus_lib.ipbus_ctrlreg_v -- reads the module ID register

     generic map (

         N_CTRL => 1,  --number of control reg

         N_STAT => 0)  --number of status reg

     port map(

       clk       => ipb_clk,

       reset     => ipb_rst,

       ipbus_in  => ipbw(N_SLV_QUAD_PHASE_CONTROL),

       ipbus_out => ipbr(N_SLV_QUAD_PHASE_CONTROL),

       d         => (others => (others => '0')) ,

       q(0)      => phase_reg,

       stb       => open);


   MGT_GT0 : entity work.gt_information

     generic map (addr_width => 8)

     port map(

       clk40            => clk40,

       BCR_in           => BCR_in,

       ipb_clk          => ipb_clk,

       rxclk280         => rxclk280(0),

       clk280           => clk280,

       ipb_rst          => ipb_rst,

       reset            => cntr_reset,

       ipb_in           => ipbw(N_SLV_GT0),

       ipb_out          => ipbr(N_SLV_GT0),

       tx_pd            => tx_pd(0),

       rx_pd            => rx_pd(0),

       --error_counter    => error_counter(15 downto 0),

       bc_cntr          => bc_cntr_0,

       bc_mux_cntr      => bc_mux_cntr_0,

       delay_cntr       => delay_cntr_0,

       not_intable      => encode_error_int(0),

       rx_resetdone     => rx_resetdone(0),

       rx_fsm_resetdone => rx_fsm_resetdone(0),

       rx_byteisaligned => rx_byteisaligned(0),

       tx_resetdone     => tx_resetdone(0),

       tx_fsm_resetdone => tx_fsm_resetdone(0),

       tx_bufstatus     => tx_bufstatus(1 downto 0),

       rx_realign       => rx_realign(0),

       rx_disperr       => rx_disperr_int(0),

       crc_error        => crc_error(0),

       mgtdata_enable   => mgtdata_enable(0),

       rxdata           => rxdata_gt0,

       rdy              => rdy(0) ,

       ram_data         => ram_data_gt0


       );


   MGT_GT1 : entity work.gt_information

     generic map (addr_width => 8)

     port map(

       clk40            => clk40,

       BCR_in           => BCR_in,

       ipb_clk          => ipb_clk,

       rxclk280         => rxclk280(1),

       clk280           => clk280,

       ipb_rst          => ipb_rst,

       reset            => cntr_reset,

       ipb_in           => ipbw(N_SLV_GT1),

       ipb_out          => ipbr(N_SLV_GT1),

       tx_pd            => tx_pd(1),

       rx_pd            => rx_pd(1),

       --error_counter    => error_counter(31 downto 16),

       bc_cntr          => bc_cntr_1,

       bc_mux_cntr      => bc_mux_cntr_1,

       delay_cntr       => delay_cntr_1,

       not_intable      => encode_error_int(1),

       rx_resetdone     => rx_resetdone(1),

       rx_fsm_resetdone => rx_fsm_resetdone(1),

       rx_byteisaligned => rx_byteisaligned(1),

       tx_resetdone     => tx_resetdone(1),

       tx_fsm_resetdone => tx_fsm_resetdone(1),

       tx_bufstatus     => tx_bufstatus(3 downto 2),

       rx_realign       => rx_realign(1),

       rx_disperr       => rx_disperr_int(1),

       crc_error        => crc_error(1),

       mgtdata_enable   => mgtdata_enable(1),

       rxdata           => rxdata_gt1,

       rdy              => rdy(1) ,

       ram_data         => ram_data_gt1


       );


   MGT_GT2 : entity work.gt_information

     generic map (addr_width => 8)

     port map(

       clk40            => clk40,

       BCR_in           => BCR_in,

       ipb_clk          => ipb_clk,

       rxclk280         => rxclk280(2),

       clk280           => clk280,

       ipb_rst          => ipb_rst,

       reset            => cntr_reset,

       ipb_in           => ipbw(N_SLV_GT2),

       ipb_out          => ipbr(N_SLV_GT2),

       tx_pd            => tx_pd(2),

       rx_pd            => rx_pd(2),

      -- error_counter    => error_counter(47 downto 32),

       bc_cntr          => bc_cntr_2,

       bc_mux_cntr      => bc_mux_cntr_2,

       delay_cntr       => delay_cntr_2,

       not_intable      => encode_error_int(2),

       rx_resetdone     => rx_resetdone(2),

       rx_fsm_resetdone => rx_fsm_resetdone(2),

       rx_byteisaligned => rx_byteisaligned(2),

       tx_resetdone     => tx_resetdone(2),

       tx_fsm_resetdone => tx_fsm_resetdone(2),

       tx_bufstatus     => tx_bufstatus(5 downto 4),

       rx_realign       => rx_realign(2),

       rx_disperr       => rx_disperr_int(2),

       crc_error        => crc_error(2),

       mgtdata_enable   => mgtdata_enable(2),

       rxdata           => rxdata_gt2,

       rdy              => rdy(2) ,

       ram_data         => ram_data_gt2


       );


   MGT_GT3 : entity work.gt_information

     generic map (addr_width => 8)

     port map(

       clk40            => clk40,

       BCR_in           => BCR_in,

       ipb_clk          => ipb_clk,

       rxclk280         => rxclk280(3),

       clk280           => clk280,

       ipb_rst          => ipb_rst,

       reset            => cntr_reset,

       ipb_in           => ipbw(N_SLV_GT3),

       ipb_out          => ipbr(N_SLV_GT3),

       tx_pd            => tx_pd(3),

       rx_pd            => rx_pd(3),

       --error_counter    => error_counter(63 downto 48),

       bc_cntr          => bc_cntr_3,

       bc_mux_cntr      => bc_mux_cntr_3,

       delay_cntr       => delay_cntr_3,

       not_intable      => encode_error_int(3),

       rx_resetdone     => rx_resetdone(3),

       rx_fsm_resetdone => rx_fsm_resetdone(3),

       rx_byteisaligned => rx_byteisaligned(3),

       tx_resetdone     => tx_resetdone(3),

       tx_fsm_resetdone => tx_fsm_resetdone(3),

       tx_bufstatus     => tx_bufstatus(7 downto 6),

       rx_realign       => rx_realign(3),

       rx_disperr       => rx_disperr_int(3),

       crc_error        => crc_error(3),

       mgtdata_enable   => mgtdata_enable(3),

       rxdata           => rxdata_gt3,

        rdy              => rdy(3) ,

       ram_data         => ram_data_gt3


       );


 end Behavioral;

gt_information
Definition: gt_information.vhd:19

gt_information.reset
in reset std_logic
reset
Definition: gt_information.vhd:27

gt_information.rx_realign
in rx_realign std_logic
rx realign status
Definition: gt_information.vhd:59

gt_information.ram_data
out ram_data std_logic_vector( 227 downto  0)
kchar generated signal ram_data from the plyback ram gt channel
Definition: gt_information.vhd:82

gt_information.clk40
in clk40 std_logic
fabric clock of 40MHz
Definition: gt_information.vhd:26

gt_information.ipb_rst
in ipb_rst std_logic
ipbus reset
Definition: gt_information.vhd:29

gt_information.BCR_in
in BCR_in std_logic
BCR from TTC information.
Definition: gt_information.vhd:24

gt_information.rx_resetdone
in rx_resetdone std_logic
rx reset done of the gt if high is done
Definition: gt_information.vhd:47

gt_information.bc_mux_cntr
in bc_mux_cntr std_logic_vector( 4 downto  0)
bc value after the mux
Definition: gt_information.vhd:37

gt_information.rx_byteisaligned
in rx_byteisaligned std_logic
rx byte alignment
Definition: gt_information.vhd:51

gt_information.rx_disperr
in rx_disperr std_logic
rx disperr error
Definition: gt_information.vhd:61

gt_information.rx_pd
in rx_pd std_logic
power control for rx side of the gt
Definition: gt_information.vhd:45

gt_information.tx_resetdone
in tx_resetdone std_logic
tx reset done of the gt if high is done
Definition: gt_information.vhd:53

gt_information.not_intable
in not_intable std_logic
not in the table
Definition: gt_information.vhd:41

gt_information.clk280
in clk280 std_logic
fabric clock 280MHz
Definition: gt_information.vhd:25

gt_information.ipb_clk
in ipb_clk std_logic
ipbus clock
Definition: gt_information.vhd:23

gt_information.rx_fsm_resetdone
in rx_fsm_resetdone std_logic
rx fsm reset done of the if high is done
Definition: gt_information.vhd:49

gt_information.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: gt_information.vhd:33

gt_information.tx_fsm_resetdone
in tx_fsm_resetdone std_logic
tx fsm reset done of the gt if high is done
Definition: gt_information.vhd:55

gt_information.tx_bufstatus
in tx_bufstatus std_logic_vector( 1 downto  0)
tx buffer status
Definition: gt_information.vhd:57

gt_information.tx_pd
in tx_pd std_logic
power control for tx side of the gt
Definition: gt_information.vhd:43

gt_information.mgtdata_enable
in mgtdata_enable std_logic
mgt enable of the channel
Definition: gt_information.vhd:72

gt_information.rxclk280
in rxclk280 std_logic
mgt rxclk
Definition: gt_information.vhd:30

gt_information.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: gt_information.vhd:31

gt_information.rxdata
in rxdata std_logic_vector( 31 downto  0)
rx_data from gt channel
Definition: gt_information.vhd:76

gt_information.bc_cntr
in bc_cntr std_logic_vector( 4 downto  0)
bc cntr value
Definition: gt_information.vhd:35

gt_information.crc_error
in crc_error std_logic
crc_error
Definition: gt_information.vhd:64

gt_information.delay_cntr
in delay_cntr std_logic_vector( 3 downto  0)
first stage delay count of gt
Definition: gt_information.vhd:39

gt_information.rdy
in rdy std_logic
ready to trigger the start of state machanie that controls the playback ram
Definition: gt_information.vhd:74

ipbus_decode_efex_mgt_quad
Definition: ipbus_decode_efex_mgt_quad.vhd:14

led_stretch
led stretch
Definition: led_stretch.vhd:12

led_stretch.clk
in clk std_logic
clock
Definition: led_stretch.vhd:17

led_stretch.input
in input std_logic
input
Definition: led_stretch.vhd:15

led_stretch.output
out output std_logic
output
Definition: led_stretch.vhd:20

mgt_quad_slaves.Behavioral
MGT quad ipbus control.
Definition: mgt_quad_slaves.vhd:132

mgt_quad_slaves
MGT quad ipbus control.
Definition: mgt_quad_slaves.vhd:18

mgt_quad_slaves.delay_cntr_2
in delay_cntr_2 std_logic_vector( 3 downto  0)
first stage delay count of gt2
Definition: mgt_quad_slaves.vhd:79

mgt_quad_slaves.qpll_lock
in qpll_lock std_logic
qpll lock of the MGT if high
Definition: mgt_quad_slaves.vhd:49

mgt_quad_slaves.mgt_enable
out mgt_enable std_logic_vector( 3 downto  0)
mgt enable of the quad
Definition: mgt_quad_slaves.vhd:85

mgt_quad_slaves.softreset_rx
out softreset_rx std_logic
rx soft reset of the quad
Definition: mgt_quad_slaves.vhd:47

mgt_quad_slaves.clk40
in clk40 std_logic
fabric clock of 40MHz
Definition: mgt_quad_slaves.vhd:27

mgt_quad_slaves.bc_cntr_1
in bc_cntr_1 std_logic_vector( 6 downto  0)
bc value of gt1
Definition: mgt_quad_slaves.vhd:61

mgt_quad_slaves.ipb_rst
in ipb_rst std_logic
ipbus reset
Definition: mgt_quad_slaves.vhd:33

mgt_quad_slaves.ram_data_gt0
out ram_data_gt0 std_logic_vector( 227 downto  0)
ram_data from the plyback ram gt0
Definition: mgt_quad_slaves.vhd:114

mgt_quad_slaves.BCR_in
in BCR_in std_logic
BCR from TTC information.
Definition: mgt_quad_slaves.vhd:29

mgt_quad_slaves.delay_cntr_1
in delay_cntr_1 std_logic_vector( 3 downto  0)
first stage delay count of gt1
Definition: mgt_quad_slaves.vhd:77

mgt_quad_slaves.rx_pd
in rx_pd std_logic_vector( 3 downto  0)
power control for rx side of the mgt
Definition: mgt_quad_slaves.vhd:55

mgt_quad_slaves.tx_resetdone
in tx_resetdone std_logic_vector( 3 downto  0)
tx reset done of the quad if high is done
Definition: mgt_quad_slaves.vhd:94

mgt_quad_slaves.rx_realign
in rx_realign std_logic_vector( 3 downto  0)
rx realign status
Definition: mgt_quad_slaves.vhd:100

mgt_quad_slaves.bc_reg_sel
out bc_reg_sel std_logic_vector( 15 downto  0)
BC level mux setting value.
Definition: mgt_quad_slaves.vhd:41

mgt_quad_slaves.crc_error
in crc_error std_logic_vector( 3 downto  0)
crc error of the quad
Definition: mgt_quad_slaves.vhd:83

mgt_quad_slaves.tx_pd
in tx_pd std_logic_vector( 3 downto  0)
power control for tx side of the mgt
Definition: mgt_quad_slaves.vhd:53

mgt_quad_slaves.bc_mux_cntr_3
in bc_mux_cntr_3 std_logic_vector( 6 downto  0)
bc value after the mux gt3
Definition: mgt_quad_slaves.vhd:73

mgt_quad_slaves.loopback
out loopback std_logic_vector( 2 downto  0)
Loopback Ports.
Definition: mgt_quad_slaves.vhd:39

mgt_quad_slaves.ram_data_gt2
out ram_data_gt2 std_logic_vector( 227 downto  0)
ram_data from the plyback ram gt2
Definition: mgt_quad_slaves.vhd:118

mgt_quad_slaves.rxclk280
in rxclk280 std_logic_vector( 3 downto  0)
rxclk
Definition: mgt_quad_slaves.vhd:25

mgt_quad_slaves.bc_cntr_0
in bc_cntr_0 std_logic_vector( 6 downto  0)
bc value of gt0
Definition: mgt_quad_slaves.vhd:59

mgt_quad_slaves.bc_mux_cntr_1
in bc_mux_cntr_1 std_logic_vector( 6 downto  0)
bc value after the mux gt1
Definition: mgt_quad_slaves.vhd:69

mgt_quad_slaves.mux_sel
out mux_sel std_logic_vector( 15 downto  0)
first stage sync mux setting value
Definition: mgt_quad_slaves.vhd:43

mgt_quad_slaves.tx_bufstatus
in tx_bufstatus std_logic_vector( 7 downto  0)
tx buffer status
Definition: mgt_quad_slaves.vhd:98

mgt_quad_slaves.delay_cntr_3
in delay_cntr_3 std_logic_vector( 3 downto  0)
first stage delay count of gt3
Definition: mgt_quad_slaves.vhd:81

mgt_quad_slaves.ram_data_gt3
out ram_data_gt3 std_logic_vector( 227 downto  0)
ram_data from the plyback ram gt3
Definition: mgt_quad_slaves.vhd:120

mgt_quad_slaves.rx_resetdone
in rx_resetdone std_logic_vector( 3 downto  0)
rx reset done of the quad if high is done
Definition: mgt_quad_slaves.vhd:88

mgt_quad_slaves.tx_fsm_resetdone
in tx_fsm_resetdone std_logic_vector( 3 downto  0)
tx fsm reset done of the quad if high is done
Definition: mgt_quad_slaves.vhd:96

mgt_quad_slaves.rx_byteisaligned
in rx_byteisaligned std_logic_vector( 3 downto  0)
RX Byte and Word Alignment.
Definition: mgt_quad_slaves.vhd:92

mgt_quad_slaves.delay_cntr_0
in delay_cntr_0 std_logic_vector( 3 downto  0)
first stage delay count of gt0
Definition: mgt_quad_slaves.vhd:75

mgt_quad_slaves.notable_error
out notable_error std_logic_vector( 3 downto  0)
notable_error
Definition: mgt_quad_slaves.vhd:127

mgt_quad_slaves.clk280
in clk280 std_logic
fabric clock 280MHz
Definition: mgt_quad_slaves.vhd:23

mgt_quad_slaves.rx_disperr
in rx_disperr std_logic_vector( 15 downto  0)
rx disperr error
Definition: mgt_quad_slaves.vhd:102

mgt_quad_slaves.ipb_clk
in ipb_clk std_logic
ipbus clock
Definition: mgt_quad_slaves.vhd:31

mgt_quad_slaves.bc_cntr_2
in bc_cntr_2 std_logic_vector( 6 downto  0)
bc value of gt2
Definition: mgt_quad_slaves.vhd:63

mgt_quad_slaves.rxdata_gt3
in rxdata_gt3 std_logic_vector( 31 downto  0)
rx_data from gt3
Definition: mgt_quad_slaves.vhd:112

mgt_quad_slaves.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: mgt_quad_slaves.vhd:37

mgt_quad_slaves.rx_fsm_resetdone
in rx_fsm_resetdone std_logic_vector( 3 downto  0)
rx fsm reset done of the quad if high is done
Definition: mgt_quad_slaves.vhd:90

mgt_quad_slaves.bc_cntr_3
in bc_cntr_3 std_logic_vector( 6 downto  0)
bc value of gt3
Definition: mgt_quad_slaves.vhd:65

mgt_quad_slaves.disperr_error
out disperr_error std_logic_vector( 3 downto  0)
disperr_error
Definition: mgt_quad_slaves.vhd:122

mgt_quad_slaves.bc_mux_cntr_0
in bc_mux_cntr_0 std_logic_vector( 6 downto  0)
bc value after the mux gt0
Definition: mgt_quad_slaves.vhd:67

mgt_quad_slaves.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: mgt_quad_slaves.vhd:35

mgt_quad_slaves.rxdata_gt0
in rxdata_gt0 std_logic_vector( 31 downto  0)
rx_data from gt0
Definition: mgt_quad_slaves.vhd:106

mgt_quad_slaves.encode_error
in encode_error std_logic_vector( 15 downto  0)
B/10B Decoder error.
Definition: mgt_quad_slaves.vhd:104

mgt_quad_slaves.bc_mux_cntr_2
in bc_mux_cntr_2 std_logic_vector( 6 downto  0)
bc value after the mux gt2
Definition: mgt_quad_slaves.vhd:71

mgt_quad_slaves.qpll_refclklost
in qpll_refclklost std_logic
qpll refrence clcok lost if high
Definition: mgt_quad_slaves.vhd:51

mgt_quad_slaves.rxdata_gt2
in rxdata_gt2 std_logic_vector( 31 downto  0)
rx_data from gt2
Definition: mgt_quad_slaves.vhd:110

mgt_quad_slaves.softreset_tx
out softreset_tx std_logic
tx soft reset of the quad
Definition: mgt_quad_slaves.vhd:45

mgt_quad_slaves.ram_data_gt1
out ram_data_gt1 std_logic_vector( 227 downto  0)
ram_data from the plyback ram gt1
Definition: mgt_quad_slaves.vhd:116

mgt_quad_slaves.rxdata_gt1
in rxdata_gt1 std_logic_vector( 31 downto  0)
rx_data from gt1
Definition: mgt_quad_slaves.vhd:108