led_stretch.vhd

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-- Pulse generator
 
library IEEE;
use IEEE.std_logic_1164.all;
 
ENTITY led_stretch IS
    PORT(
    input   : in    std_logic;
    clk     : in    std_logic;
    output  : out   std_logic
    );
END led_stretch ;
ARCHITECTURE rtl OF led_stretch IS
 
signal Reg1,Reg2        : std_logic := '0';
 
 
BEGIN
 
  process (clk)
     
    begin 
     
        if rising_edge(clk) THEN
          Reg1 <= input;
          Reg2 <= Reg1;
      end if;
      
      end process; 
      
output <= Reg2;
      
 
 
END rtl;