mgt_quad_slaves Entity Reference

MGT quad ipbus control. More...

Inheritance diagram for mgt_quad_slaves:

Entities
Behavioral	architecture
	MGT quad ipbus control. More...

Libraries
IEEE
ipbus_lib

Use Clauses
STD_LOGIC_1164
numeric_std
ipbus
ipbus_decode_efex_mgt_quad	Package <ipbus_decode_efex_mgt_quad>

Generics
ENABLE	std_logic := ' 1 '

Ports
clk280	in	std_logic
		fabric clock 280MHz
rxclk280	in	std_logic_vector ( 3 downto 0 )
		rxclk
clk40	in	std_logic
		fabric clock of 40MHz
BCR_in	in	std_logic
		BCR from TTC information.
ipb_clk	in	std_logic
		ipbus clock
ipb_rst	in	std_logic
		ipbus reset
ipb_in	in	ipb_wbus
		IPBus input bus going from master to slaves.
ipb_out	out	ipb_rbus
		IPBus output bus going from slaves to master.
loopback	out	std_logic_vector ( 2 downto 0 )
		Loopback Ports.
bc_reg_sel	out	std_logic_vector ( 15 downto 0 )
		BC level mux setting value.
mux_sel	out	std_logic_vector ( 15 downto 0 )
		first stage sync mux setting value
softreset_tx	out	std_logic
		tx soft reset of the quad
softreset_rx	out	std_logic
		rx soft reset of the quad
qpll_lock	in	std_logic
		qpll lock of the MGT if high
qpll_refclklost	in	std_logic
		qpll refrence clcok lost if high
tx_pd	in	std_logic_vector ( 3 downto 0 )
		power control for tx side of the mgt
rx_pd	in	std_logic_vector ( 3 downto 0 )
		power control for rx side of the mgt
bc_cntr_0	in	std_logic_vector ( 6 downto 0 )
		bc value of gt0
bc_cntr_1	in	std_logic_vector ( 6 downto 0 )
		bc value of gt1
bc_cntr_2	in	std_logic_vector ( 6 downto 0 )
		bc value of gt2
bc_cntr_3	in	std_logic_vector ( 6 downto 0 )
		bc value of gt3
bc_mux_cntr_0	in	std_logic_vector ( 6 downto 0 )
		bc value after the mux gt0
bc_mux_cntr_1	in	std_logic_vector ( 6 downto 0 )
		bc value after the mux gt1
bc_mux_cntr_2	in	std_logic_vector ( 6 downto 0 )
		bc value after the mux gt2
bc_mux_cntr_3	in	std_logic_vector ( 6 downto 0 )
		bc value after the mux gt3
delay_cntr_0	in	std_logic_vector ( 3 downto 0 )
		first stage delay count of gt0
delay_cntr_1	in	std_logic_vector ( 3 downto 0 )
		first stage delay count of gt1
delay_cntr_2	in	std_logic_vector ( 3 downto 0 )
		first stage delay count of gt2
delay_cntr_3	in	std_logic_vector ( 3 downto 0 )
		first stage delay count of gt3
crc_error	in	std_logic_vector ( 3 downto 0 )
		crc error of the quad
mgt_enable	out	std_logic_vector ( 3 downto 0 )
		mgt enable of the quad
phase_mux	out	std_logic_vector ( 15 downto 0 )
rx_resetdone	in	std_logic_vector ( 3 downto 0 )
		rx reset done of the quad if high is done
rx_fsm_resetdone	in	std_logic_vector ( 3 downto 0 )
		rx fsm reset done of the quad if high is done
rx_byteisaligned	in	std_logic_vector ( 3 downto 0 )
		RX Byte and Word Alignment.
tx_resetdone	in	std_logic_vector ( 3 downto 0 )
		tx reset done of the quad if high is done
tx_fsm_resetdone	in	std_logic_vector ( 3 downto 0 )
		tx fsm reset done of the quad if high is done
tx_bufstatus	in	std_logic_vector ( 7 downto 0 )
		tx buffer status
rx_realign	in	std_logic_vector ( 3 downto 0 )
		rx realign status
rx_disperr	in	std_logic_vector ( 15 downto 0 )
		rx disperr error
encode_error	in	std_logic_vector ( 15 downto 0 )
		B/10B Decoder error.
rxdata_gt0	in	std_logic_vector ( 31 downto 0 )
		rx_data from gt0
rxdata_gt1	in	std_logic_vector ( 31 downto 0 )
		rx_data from gt1
rxdata_gt2	in	std_logic_vector ( 31 downto 0 )
		rx_data from gt2
rxdata_gt3	in	std_logic_vector ( 31 downto 0 )
		rx_data from gt3
ram_data_gt0	out	std_logic_vector ( 227 downto 0 )
		ram_data from the plyback ram gt0
ram_data_gt1	out	std_logic_vector ( 227 downto 0 )
		ram_data from the plyback ram gt1
ram_data_gt2	out	std_logic_vector ( 227 downto 0 )
		ram_data from the plyback ram gt2
ram_data_gt3	out	std_logic_vector ( 227 downto 0 )
		ram_data from the plyback ram gt3
disperr_error	out	std_logic_vector ( 3 downto 0 )
		disperr_error
notable_error	out	std_logic_vector ( 3 downto 0 )
		notable_error

Detailed Description

MGT quad ipbus control.

Module connects the quad mgts to the ipbus registers for status and control of the quad if is enabled Each MGT connects directly to their registers for control and status. If the quad is not enabled then it will return deadbeef through the ipbus

Author

Mohammed Syiad

Francesco Gonnella

Definition at line 18 of file mgt_quad_slaves.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_quad_slaves.vhd