Clock generating module. More...

Inheritance diagram for clk_resources:

Entities
Behavioral	architecture
	Clock generating module. More...

Ports
gt_clk_p	in	std_logic
		Crystal clock input 125MHz.
gt_clk_n	in	std_logic
		Crystal clock input 125MHz.
TTC_clk_p	in	std_logic
		TTC clock input 40MHz.
TTC_clk_n	in	std_logic
		TTC clock input 40MHz.
reset_clk125	in	std_logic
		External reset signal for 125 MHz clock domain from Control FPGA.
clk40_rdout	out	std_logic
		40MHz clock output dedicated to Readout Logic
clk200	out	std_logic
		200MHz clock output (TTC)
clk40	out	std_logic
		40MHz clock output
clk280	out	std_logic
		280MHz clock output
rst_macclk	out	std_logic
		Reset output synchronised to mac clock.
onehz	out	std_logic
		One Hz clock output.
reset	in	std_logic
		Reset output generated from TTC clock MMCM.
rst_ipb	out	std_logic
		Reset output synchronised to ipbus clock.
load	out	std_logic
		40MHz clock output with 12% duty cycle used in ALGO Block
mac_clk	out	std_logic
		125MHz clock output for ipbus communication between FPGAs
locked_40m	out	std_logic
		40MHz clock Locked output
ipb_clk	out	std_logic
		31.25MHz clock output used for ipbus communication and accessing registers
clk200_iodelay	out	std_logic
		Pure 200MHz clock output.

Detailed Description

Clock generating module.

This module contains the clock wizard modules used to generate all the clocks in the design.

ClockWizard module takes 40MHz crystal or TTC clock as input and generates 40MHz, 200MHz and 280MHz output clocks.
clk_wiz_1 module takes 40MHz clock from ClockWizard module as input and generates 40MHz output clock to be used by the Readout Logic.
clocks_7s_extphy module takes 125MHz crystal clock as input and generates 125MHz and 31.25MHz output clocks and resets.

Definition at line 25 of file clk_resources.vhd.

The documentation for this class was generated from the following file:

Entities