clk_resources.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library ipbus_lib;
use ipbus_lib.ipbus.all;
entity clk_resources is
  port (
    gt_clk_p   : in  std_logic;
    gt_clk_n   : in  std_logic;
    TTC_clk_p  : in  std_logic;
    TTC_clk_n  : in  std_logic;
    reset_clk125 : in  std_logic;
    clk40_rdout  : out std_logic;
    clk200     : out std_logic;
    clk40      : out std_logic;
    clk280     : out std_logic;
    rst_macclk : out std_logic;
    onehz      : out std_logic;  -- this goes to the led_clk of the configure block
    reset      : in  std_logic; -- to reset the mmcm of the 280M fabric clock
    rst_ipb    : out std_logic;
    load       : out std_logic;  -- goes to the top level of the algo block
    mac_clk    : out std_logic;
    locked_40m : out std_logic;    -- use this as this gets its clock from 40Mz signal
    ipb_clk    : out std_logic;
    clk200_iodelay : out std_logic
    );
end clk_resources;
 
architecture Behavioral of clk_resources is
 
  component clk_wiz_1
    port
      (clk40       : in  std_logic;
       clk40_rdout : out std_logic;
       reset       : in  std_logic;
       locked      : out std_logic
       );
  end component;
 
 
  component ClockWizard
    port
      (clk200    : out std_logic;
       load      : out std_logic;
       reset     : in  std_logic;
       clk40     : out std_logic;
       clk280    : out std_logic;
       locked    : out std_logic;
       clk_in1_p : in  std_logic;
       clk_in1_n : in  std_logic
       );
  end component;
 
  component clocks_7s_extphy
    port(
        sysclk_p: in std_logic;
        sysclk_n: in std_logic;
        clko_125: out std_logic;
        clko_200: out std_logic;
        clko_ipb: out std_logic;
        locked: out std_logic;
        nuke: in std_logic := '0';
        soft_rst: in std_logic := '0';
        rsto_125: out std_logic;
        rsto_ipb: out std_logic;
        rsto_ipb_ctrl: out std_logic;
        onehz: out std_logic
    );
  end component;
 
  signal clk40_int, mac_clk_int : std_logic;
  signal rsto_eth  : std_logic := '1';
  signal locked    : std_logic := '0';
 
begin
 
  mac_clk <= mac_clk_int;
 
  Inputclk40M : ClockWizard
    port map (
 
      -- Clock in ports
      clk_in1_p => TTC_clk_p,
      clk_in1_n => TTC_clk_n,
      -- Clock out ports
      clk200    => clk200,
      clk40     => clk40_int,
      clk280    => clk280,
      reset     => reset,
      load      => load,
      -- Status and control signals
      locked    => locked_40m
      );
 
  clk40_gen : clk_wiz_1
    port map (
 
      -- Clock out ports
      clk40_rdout => clk40_rdout,
      -- Status and control signals
      reset  => '0',
      locked => open,
      -- Clock in ports
      clk40  => clk40_int
      );
 
  clk40 <= clk40_int;
 
  --    DCM clock generation for internal bus, ethernet
  clocks : clocks_7s_extphy
    port map(
      sysclk_p      => gt_clk_p,
      sysclk_n      => gt_clk_n,
      clko_125      => mac_clk_int,
      clko_200      => clk200_iodelay,
      clko_ipb      => ipb_clk,
      locked        => locked,
      soft_rst      => reset_clk125,    --soft_rst now for ethernet clock
      rsto_125      => rsto_eth,
      rsto_ipb      => rst_ipb,
      rsto_ipb_ctrl => open,
      onehz         => onehz
      );
 
  process(mac_clk_int)
  begin
    if rising_edge(mac_clk_int) then
      rst_macclk <= rsto_eth;
    end if;
  end process;
 
end Behavioral;