clocks_7s_extphy Entity Reference

Inheritance diagram for clocks_7s_extphy:

Entities
rtl	architecture

Libraries
ipbus_lib
ieee
unisim

Use Clauses
all
std_logic_1164
numeric_std
VComponents

Ports
sysclk_p	in	std_logic
sysclk_n	in	std_logic
clko_125	out	std_logic
clko_200	out	std_logic
clko_ipb	out	std_logic
locked	out	std_logic
nuke	in	std_logic := ' 0 '
soft_rst	in	std_logic := ' 0 '
rsto_125	out	std_logic
rsto_ipb	out	std_logic
rsto_ipb_ctrl	out	std_logic
onehz	out	std_logic

Detailed Description

Definition at line 23 of file clocks_7s_extphy.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd