rtl Architecture Reference

Processes
PROCESS_36	( sysclk )
PROCESS_37	( clk_ipb_b )
PROCESS_38	( clk_ipb_b )
PROCESS_39	( clk_125_b )

Signals
dcm_locked	std_logic
sysclk	std_logic
clk_200	std_logic
clk_ipb_i	std_logic
clk_125_i	std_logic
clkfb	std_logic
clk_ipb_b	std_logic
clk_125_b	std_logic
d17	std_logic
d17_d	std_logic
nuke_i	std_logic := ' 0 '
nuke_d	std_logic := ' 0 '
nuke_d2	std_logic := ' 0 '
rst	std_logic := ' 1 '
srst	std_logic := ' 1 '
rst_ipb	std_logic := ' 1 '
rst_125	std_logic := ' 1 '
rst_ipb_ctrl	std_logic := ' 1 '
rctr	unsigned ( 3 downto 0 ) := " 0000 "

Instantiations
ibufgds0	ibufgds
bufg200	bufg
bufg125	bufg
bufgipb	bufg
mmcm	mmcme2_base
clkdiv	ipbus_clock_div

Detailed Description

Definition at line 41 of file clocks_7s_extphy.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/clocks/clocks_7s_extphy.vhd