clocks_7s_extphy.vhd

-- clocks_7s_extphy
--
-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 200MHz reference
-- Also an unbuffered 200MHz clock for IO delay calibration block
-- Includes reset logic for ipbus
--
-- Dave Newbold, April 2011
--
-- Updated for eFEX to use 125MHz reference and produce buffered 200MHz clock
-- and soft reset now mapped to 125 MHz domain
--
-- $Id$
 
library ipbus_lib;
use ipbus_lib.all;
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.VComponents.all;
 
entity clocks_7s_extphy is
    port(
        sysclk_p: in std_logic; 
        sysclk_n: in std_logic;
        clko_125: out std_logic;
        clko_200: out std_logic;
        clko_ipb: out std_logic;
        locked: out std_logic;
        nuke: in std_logic := '0';
        soft_rst: in std_logic := '0';
        rsto_125: out std_logic;
        rsto_ipb: out std_logic;
        rsto_ipb_ctrl: out std_logic;
        onehz: out std_logic
    );
 
end clocks_7s_extphy;
 
architecture rtl of clocks_7s_extphy is
    
    signal dcm_locked, sysclk,clk_200, clk_ipb_i, clk_125_i, clkfb, clk_ipb_b, clk_125_b: std_logic;
    signal d17, d17_d: std_logic;
    signal nuke_i, nuke_d, nuke_d2: std_logic := '0';
    signal rst, srst, rst_ipb, rst_125, rst_ipb_ctrl: std_logic := '1';
    signal rctr: unsigned(3 downto 0) := "0000";
 
begin
 
    ibufgds0: IBUFGDS port map(
        i => sysclk_p,
        ib => sysclk_n,
        o => sysclk
    );
 
    bufg200: BUFG port map(
            i => clk_200,
            o => clko_200
        );
 
    bufg125: BUFG port map(
        i => clk_125_i,
        o => clk_125_b
    );
 
    clko_125 <= clk_125_b;
 
    bufgipb: BUFG port map(
        i => clk_ipb_i,
        o => clk_ipb_b
    );
 
    clko_ipb <= clk_ipb_b;
 
    mmcm: MMCME2_BASE
        generic map(
            clkfbout_mult_f => 8.0,
            clkout1_divide => 8,
            clkout2_divide => 32,
            clkout3_divide => 5,
            clkin1_period => 8.0
        )
        port map(
            clkin1 => sysclk,
            clkfbin => clkfb,
            clkfbout => clkfb,
            clkout1 => clk_125_i,
            clkout2 => clk_ipb_i,
            clkout3 => clk_200,
            locked => dcm_locked,
            rst => '0',
            pwrdwn => '0'
        );
    
    clkdiv: entity ipbus_lib.ipbus_clock_div
    port map(
        clk => sysclk,
        d17 => d17,
        d28 => onehz
    );
    
    process(sysclk)
    begin
        if rising_edge(sysclk) then
            d17_d <= d17;
            if d17='1' and d17_d='0' then
                rst <= nuke_d2 or not dcm_locked;
                nuke_d <= nuke_i; -- Time bomb (allows return packet to be sent)
                nuke_d2 <= nuke_d;
            end if;
        end if;
    end process;
        
    locked <= dcm_locked;
    
    process(clk_ipb_b)
    begin
        if rising_edge(clk_ipb_b) then
            rst_ipb <= rst;
            nuke_i <= nuke;
        end if;
    end process;
    
    rsto_ipb <= rst_ipb;
    
    process(clk_ipb_b)
    begin
        if rising_edge(clk_ipb_b) then
            rst_ipb_ctrl <= rst;
        end if;
    end process;
    
    rsto_ipb_ctrl <= rst_ipb_ctrl;
    
    srst <= '1' when rctr /= "0000" else '0';
 
    process(clk_125_b)
    begin
        if rising_edge(clk_125_b) then
            rst_125 <= rst or srst;
            if srst = '1' or soft_rst = '1' then
                rctr <= rctr + 1;
            end if;
        end if;
    end process;
    
    rsto_125 <= rst_125;
 
end rtl;