Behavioral Architecture Reference

Clock generating module. More...

Processes
PROCESS_53	( mac_clk_int )

Components
clk_wiz_1
ClockWizard
clocks_7s_extphy	<Entity clocks_7s_extphy>

Signals
clk40_int	std_logic
mac_clk_int	std_logic
rsto_eth	std_logic := ' 1 '
locked	std_logic := ' 0 '

Instantiations
inputclk40m	clockwizard
clk40_gen	clk_wiz_1
clocks	clocks_7s_extphy <Entity clocks_7s_extphy>

Detailed Description

Clock generating module.

This module contains the clock wizard modules used to generate all the clocks in the design.

• ClockWizard module takes 40MHz crystal or TTC clock as input and generates 40MHz, 200MHz and 280MHz output clocks.
• clk_wiz_1 module takes 40MHz clock from ClockWizard module as input and generates 40MHz output clock to be used by the Readout Logic.
• clocks_7s_extphy module takes 125MHz crystal clock as input and generates 125MHz and 31.25MHz output clocks and resets.

Author

Mohammed Siyad

Saeed Taghavi

Definition at line 67 of file clk_resources.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Clock_Resources/clk_resources.vhd