FPGA Self Reconfigure module. More...

Inheritance diagram for self_configure:

Entities
rtl	architecture
	FPGA Self Reconfigure module. More...

Libraries
ieee

Use Clauses
std_logic_1164

Ports
WBSTAR	in	std_logic_vector ( 31 downto 0 )
		Warm Boot Start Address.
clk	in	std_logic
		Clock input to ICAP 31.25MHz.
reset	in	std_logic
		Reset input.
trigger	in	std_logic
		Trigger input to start reconfigureation of the FPGA from the WBSTAR.
indicator	out	std_logic
		Indicator output signal connected to LED on front panel of eFEX card.

Detailed Description

FPGA Self Reconfigure module.

This module provides the interface to necessary registers for reconfiguring the FPGA through ipbus.

The WBSTAR value is written through the ipbus register reconfigure,

This is set to 0X20000 to load the user image, or
This is set to 0X0 to load the golden image. The trigger signal is applied by writing value 1 to bit 30 of ipbus register module_control.

Definition at line 19 of file self_configure.vhd.

The documentation for this class was generated from the following file:

Entities