official/Doc/self__configure_8vhd_source.html

 library ieee;

 use ieee.std_logic_1164.all;


 entity self_configure is

   port(

     WBSTAR    : in  std_logic_vector(31 downto 0);

     clk       : in  std_logic;  --icap_clk,

     reset     : in  std_logic;

     trigger   : in  std_logic;

     indicator : out std_logic

     );


 end self_configure;


 architecture rtl of self_configure is


 begin


   config : entity work.reconfig

     port map(

       WBSTAR  => WBSTAR,        -- Warm Boot Start Address

       trigger => trigger,

       sysclk  => clk

       );


   indicator <= '0';


 end rtl;


reconfig
FPGA Reconfiguration State Machine.
Definition: reconfig.vhd:25

reconfig.WBSTAR
in WBSTAR std_logic_vector( 31 downto  0)
Warm Boot Start Address.
Definition: reconfig.vhd:29

self_configure.rtl
FPGA Self Reconfigure module.
Definition: self_configure.vhd:36

self_configure
FPGA Self Reconfigure module.
Definition: self_configure.vhd:19

self_configure.reset
in reset std_logic
Reset input.
Definition: self_configure.vhd:26

self_configure.clk
in clk std_logic
Clock input to ICAP 31.25MHz.
Definition: self_configure.vhd:24

self_configure.indicator
out indicator std_logic
Indicator output signal connected to LED on front panel of eFEX card.
Definition: self_configure.vhd:31

self_configure.WBSTAR
in WBSTAR std_logic_vector( 31 downto  0)
Warm Boot Start Address.
Definition: self_configure.vhd:22

self_configure.trigger
in trigger std_logic
Trigger input to start reconfigureation of the FPGA from the WBSTAR.
Definition: self_configure.vhd:28