reconfig Entity Reference

FPGA Reconfiguration State Machine. More...

Inheritance diagram for reconfig:

Entities
behavioral	architecture
	FPGA Reconfiguration State Machine. More...

Libraries
IEEE
UNISIM

Use Clauses
STD_LOGIC_1164
numeric_std
vcomponents

Generics
MAX_COUNT	integer := 65535

Ports
WBSTAR	in	std_logic_vector ( 31 downto 0 )
		Warm Boot Start Address.
TRIGGER	in	std_logic
		Trigger input to start reconfigureation of the FPGA from the WBSTAR.
SYSCLK	in	std_logic
		Clock input to ICAP 31.25MHz.

Detailed Description

FPGA Reconfiguration State Machine.

This module provides the state machine necessary to control the Xilinx ICAP IP

The WBSTAR value is written through the ipbus register reconfigure,

• This is set to 0X20000 to load the user image, or
• This is set to 0X0 to load the golden image. The trigger signal is applied by writing value 1 to bit 30 of ipbus register module_control.

The state machine writes a series of commands to set up the ICAP and start reconfiguration of the fpga from the SPI Flash memory from the WBSTAR location.

Author

Mohammed Siyad

Saeed Taghavi

Definition at line 25 of file reconfig.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd