behavioral Architecture Reference

FPGA Reconfiguration State Machine. More...

Processes
PROCESS_70	( SYSCLK )
PROCESS_71	( SYSCLK )

Types
FSM_STATE	( IDLE , DATA_00 , DATA_01 , DATA_02 , DATA_03 , DATA_04 , DATA_05 , DATA_06 , DATA_07 )

Signals
NEXT_STATE	FSM_STATE := IDLE
CE_n	std_logic := ' 1 '
ICAP_DATA	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ICAP_WRITE_n	std_logic := ' 1 '
ICAP_DATA_BITSWAP	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
reconfig_delay	integer range 0 to MAX_COUNT := 0
trigger_reconfig	std_logic := ' 0 '

Attributes
dont_touch	string
dont_touch	signal is " true "

Instantiations
icape2_inst	icape2

Detailed Description

FPGA Reconfiguration State Machine.

This module provides the state machine necessary to control the Xilinx ICAP IP

The WBSTAR value is written through the ipbus register reconfigure,

• This is set to 0X20000 to load the user image, or
• This is set to 0X0 to load the golden image. The trigger signal is applied by writing value 1 to bit 30 of ipbus register module_control.

The state machine writes a series of commands to set up the ICAP and start reconfiguration of the fpga from the SPI Flash memory from the WBSTAR location.

Author

Mohammed Siyad

Saeed Taghavi

Definition at line 38 of file reconfig.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/reconfig.vhd