IPBusTopMergingModule Entity Reference

Top of TOB merging module with IPBus interface. More...

Inheritance diagram for IPBusTopMergingModule:

Entities
Behavioral	architecture
	Top of TOB merging module with IPBus interface. More...

Libraries
IEEE
work
ipbus_lib

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
ipbus_decode_efex_merging
DataTypes	Package <DataTypes>
AlgoDataTypes	Package <AlgoDataTypes>
ipbus_reg_types
ipbus

Generics
TEST	boolean := false
ENABLE	std_logic := ' 1 '

Ports
CLK	in	std_logic
IN_Data	in	AlgoTriggerObjects ( 3 downto 0 )
IN_Sync	in	std_logic
IN_BCN_sync	in	std_logic_vector ( 3 downto 0 )
IN_local_BCN	in	std_logic_vector ( 11 downto 0 )
OUT_merged_BCN	out	std_logic_vector ( 11 downto 0 )
ipb_clk	in	std_logic
ipb_rst	in	std_logic
ipb_in	in	ipb_wbus
ipb_out	out	ipb_rbus
OUT_Sync	out	std_logic
OUT_Valid	out	std_logic
OUT_TOB	out	AlgoTriggerObject

Detailed Description

Top of TOB merging module with IPBus interface.

This module is an IPBus-capable wrapper of TopSorting Modules. It merges the local TOBs together with the TOBs coming from the other 3 FPGAs. It contains 1 4-input sorting modules, 4 input and 1 output spyRAMs, all ipbus controlled.

Author

Francesco Gonnella

Definition at line 25 of file IPBusTopMergingModule.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/IPBusTopMergingModule.vhd