Behavioral Architecture Reference

Top of TOB merging module with IPBus interface. More...

Processes
BCN_FPGA_sych	( CLK )
BCN_published_ipbus	( CLK )
local_BCN_delay	( CLK )

Constants
N_CTRL	positive := 3
N_STAT	positive := 2

Types
BCN_t	( 6 downto 0 ) std_logic_vector ( 11 downto 0 )

Signals
ipb_to_slaves	ipb_wbus_array ( N_SLAVES- 1 downto 0 )
ipb_from_slaves	ipb_rbus_array ( N_SLAVES- 1 downto 0 ) := ( others = > IPB_RBUS_NULL )
write_reg	ipb_reg_v ( N_STAT- 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
read_reg	ipb_reg_v ( N_CTRL- 1 downto 0 )
regMergingControl	AlgoRegister
regInternalSortingControl	AlgoRegister
regMergingStatus	AlgoRegister
regOffset	AlgoRegister
MergingStart	std_logic
MergedStart	std_logic
MergedWrite	std_logic
MergedData	AlgoTriggerObject
MergedDataOut	AlgoTriggerObject
MergingDataIn	AlgoTriggerObjects ( 3 downto 0 )
	Input data before offset.
OffsetData	AlgoTriggerObjects ( 3 downto 0 )
	Input data after offset, before demux.
MergingData	AlgoTriggerObjects ( 3 downto 0 )
	Input data after demux.
InputRAMOut	AlgoTriggerObjects ( 3 downto 0 )
FakeInputEnable	std_logic := ' 0 '
SpyInputEnable	std_logic := ' 0 '
OutputRAMOut	AlgoTriggerObject
FakeOutputEnable	std_logic := ' 0 '
SpyOutputEnable	std_logic := ' 0 '
Offset0	std_logic_vector ( 5 downto 0 )
Offset1	std_logic_vector ( 5 downto 0 )
Offset2	std_logic_vector ( 5 downto 0 )
Offset3	std_logic_vector ( 5 downto 0 )
Enable0	std_logic
Enable1	std_logic
Enable2	std_logic
Enable3	std_logic
bcn_sync	std_logic
BCN_cnt3	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
BCN_cnt2	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
BCN_cnt1	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
BCN_cnt0	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
BCN_done	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
BCN_counters	std_logic_vector ( 29 downto 0 ) := ( others = > ' 0 ' )
reset_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
merged_bcn_d1	std_logic_vector ( 11 downto 0 )
merged_bcn_d2	std_logic_vector ( 11 downto 0 )
TOB_BCN_d	BCN_t := ( others = > ( others = > ' 0 ' ) )

Instantiations
ipbus_fabric	ipbus_fabric_sel
ipbus_fabric	ipbus_fabric_sel
ipbus_merging_registers	ipbus_ctrlreg_v
tob_synch_offset	TOB_synch <Entity TOB_synch>
tobmerging	TopSortingModule <Entity TopSortingModule>
inputram_1	ipbus_sorting_outputRAM_wrapper <Entity ipbus_sorting_outputRAM_wrapper>
inputram_2	ipbus_sorting_outputRAM_wrapper <Entity ipbus_sorting_outputRAM_wrapper>
inputram_3	ipbus_sorting_outputRAM_wrapper <Entity ipbus_sorting_outputRAM_wrapper>
inputram_4	ipbus_sorting_outputRAM_wrapper <Entity ipbus_sorting_outputRAM_wrapper>
outputram	ipbus_sorting_outputRAM_wrapper <Entity ipbus_sorting_outputRAM_wrapper>

Detailed Description

Top of TOB merging module with IPBus interface.

This module is an IPBus-capable wrapper of TopSorting Modules. It merges the local TOBs together with the TOBs coming from the other 3 FPGAs. It contains 1 4-input sorting modules, 4 input and 1 output spyRAMs, all ipbus controlled.

Author

Francesco Gonnella

Definition at line 52 of file IPBusTopMergingModule.vhd.

---

The documentation for this class was generated from the following file:

• Algorithm/hdl/IPBusTopMergingModule.vhd