eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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top_efex_processor.vhd
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1 
68 
69 library IEEE;
70 use IEEE.STD_LOGIC_1164.all;
71 use ieee.numeric_std.all;
72 library unisim;
73 use unisim.VComponents.all;
74 
75 library algolib;
76 use algolib.AlgoDataTypes.all;
77 library ipbus_lib;
78 use ipbus_lib.ipbus.all;
79 
80 library infrastructure_lib;
81 use infrastructure_lib.all;
82 use infrastructure_lib.ipbus_decode_L1CaloEfexProcessor.all;
83 use infrastructure_lib.synch_type.all;
84 use infrastructure_lib.EfexDataFormats.all;
85 use infrastructure_lib.mgt_type.all;
86 use infrastructure_lib.ProcessorFPGAPackage.all;
87 
88 library TOB_rdout_lib;
89 use TOB_rdout_lib.TOB_rdout_ip_pkg.all;
90 use tob_rdout_lib.data_type_pkg.all;
91 use tob_rdout_lib.tob_rdout_comp_pkg.all;
92 
93 use infrastructure_lib.golden.all;
94 
96 entity top_efex_processor is
97  generic(
99  FLAVOUR : integer := 0;
101  GLOBAL_DATE : std_logic_vector(31 downto 0) := x"00000000";
103  GLOBAL_TIME : std_logic_vector(31 downto 0) := x"00000000";
105  GLOBAL_SHA : std_logic_vector(31 downto 0) := x"00000000";
107  GLOBAL_VER : std_logic_vector(31 downto 0) := x"00000000";
108 
110  TOP_SHA : std_logic_vector(31 downto 0) := x"00000000";
112  TOP_VER : std_logic_vector(31 downto 0) := x"00000000";
113 
115  CON_SHA : std_logic_vector(31 downto 0) := x"00000000";
117  CON_VER : std_logic_vector(31 downto 0) := x"00000000";
118 
120  XML_SHA : std_logic_vector(31 downto 0) := x"00000000";
122 
123  XML_VER : std_logic_vector(31 downto 0) := x"00000000";
124 
126  HOG_SHA : std_logic_vector(31 downto 0) := x"00000000";
128  HOG_VER : std_logic_vector(31 downto 0) := x"00000000";
129 
131  ALGOLIB_SHA : std_logic_vector(31 downto 0) := x"00000000";
133  ALGOLIB_VER : std_logic_vector(31 downto 0) := x"00000000";
134 
136  INFRASTRUCTURE_LIB_SHA : std_logic_vector(31 downto 0) := x"00000000";
138  INFRASTRUCTURE_LIB_VER : std_logic_vector(31 downto 0) := x"00000000";
139 
141  TOB_RDOUT_LIB_SHA : std_logic_vector(31 downto 0) := x"00000000";
143  TOB_RDOUT_LIB_VER : std_logic_vector(31 downto 0) := x"00000000";
144 
146  IPBUS_LIB_SHA : std_logic_vector(31 downto 0) := x"00000000";
148  IPBUS_LIB_VER : std_logic_vector(31 downto 0) := x"00000000";
149 
150  -- Firmware parameters
151  READOUT_ENABLED : boolean := true;
152  INPUT_RAM_ENABLED : boolean := false;
153  OUTPUT_RAMS_ENABLED : boolean := false;
154  SORT_IN_RAM_ENABLED : boolean := false;
155  SORT_OUT_RAM_ENABLED : boolean := false;
156  MGT_ENABLED : boolean := true;
157  MERGE_ENABLED : boolean := true;
158  DATA_PATH_ENABLED : boolean := true;
159 
160  TAU_ALGO_VERSION : std_logic_vector(1 downto 0) := "10"; -- any non 0 is BDT
161  EG_ALGO_VERSION : std_logic_vector(1 downto 0) := "01"; -- this includes Richard's 2025 study and fast multiplers
162 
164  ENCODING_MODE : integer := 2; -- Enable Standard multi linear encdoing, 2 Enable Steve's encoding
165 
167  EFEX_POSITION : integer := 0; -- Enable dynamic mapping
168 
169 
170  n_channels : natural := 64);
171 
172  port (
173  -- These ports are common between user and golden images and are constrained in golden_fpga*.xdc
174  gt_clk125_p : in std_logic;
175  gt_clk125_n : in std_logic;
176  master_rx_data : in std_logic_vector (9 downto 0);
177  master_tx_pause : in std_logic;
178  master_tx_data : out std_logic_vector (9 downto 0);
179  flash_csn : out std_logic;
180  flash_mosi : out std_logic;
181  flash_miso : in std_logic;
182  flash_led : out std_logic;
183  ttc_clk_p : in std_logic; -- !ttc clock 40Mhz
184  ttc_clk_n : in std_logic; -- !ttc clock 40Mhz
185  reset_clk125 : in std_logic;
186  hardware_addr : in std_logic_vector (11 downto 0);
187  fpga_geo_addr : in std_logic_vector (1 downto 0);
188 
189  VAUXP, VAUXN : in std_logic;
190  Vp, Vn : in std_logic;
191 
192  -- Input and output ports present in user images but not in golden images should be defined inside the following records in the golden package in user.vhd
193  -- When adding/removing a port you need to, update the P_RECORD_TO_PORTS function and relative signals
194 
195  efex_in : in efex_processor_input;
196  efex_out : out efex_processor_output
197  );
198 
199 end top_efex_processor;
200 
202 architecture Behavioral of top_efex_processor is
203 
204 ------------------------------------------------
205 
206  component io_delay
207  generic
208  ( -- width of the data for the system
209  SYS_W : integer := 16;
210  -- width of the data for the device
211  DEV_W : integer := 16);
212  port
213  (
214  -- From the system into the device
215  data_in_from_pins_p : in std_logic_vector(SYS_W-1 downto 0);
216  data_in_from_pins_n : in std_logic_vector(SYS_W-1 downto 0);
217  data_in_to_device : out std_logic_vector(DEV_W-1 downto 0);
218 
219 -- Input, Output delay control signals
220  delay_clk : in std_logic;
221  in_delay_reset : in std_logic; -- Active high synchronous reset for input delay
222  in_delay_data_ce : in std_logic_vector(SYS_W -1 downto 0); -- Enable signal for delay
223  in_delay_data_inc : in std_logic_vector(SYS_W -1 downto 0); -- Delay increment (high), decrement (low) signal
224  in_delay_tap_in : in std_logic_vector(5*SYS_W -1 downto 0); -- Dynamically loadable delay tap value for input delay
225  in_delay_tap_out : out std_logic_vector(5*SYS_W -1 downto 0); -- Delay tap value for monitoring input delay
226  delay_locked : out std_logic; -- Locked signal from IDELAYCTRL
227  ref_clock : in std_logic; -- Reference Clock for IDELAYCTRL. Has to come from BUFG.
228 
229 -- Clock and reset signals
230  clk_in : in std_logic; -- Fast clock from PLL/MMCM
231  io_reset : in std_logic); -- Reset signal for IO circuit
232  end component;
233 
234  component io_delay2
235  generic
236  ( -- width of the data for the system
237  SYS_W : integer := 1;
238  -- width of the data for the device
239  DEV_W : integer := 1);
240  port
241  (
242  -- From the system into the device
243  data_in_from_pins_p : in std_logic_vector(SYS_W-1 downto 0);
244  data_in_from_pins_n : in std_logic_vector(SYS_W-1 downto 0);
245  data_in_to_device : out std_logic_vector(DEV_W-1 downto 0);
246 
247 -- Input, Output delay control signals
248  delay_clk : in std_logic;
249  in_delay_reset : in std_logic; -- Active high synchronous reset for input delay
250  in_delay_data_ce : in std_logic_vector(SYS_W -1 downto 0); -- Enable signal for delay
251  in_delay_data_inc : in std_logic_vector(SYS_W -1 downto 0); -- Delay increment (high), decrement (low) signal
252  in_delay_tap_in : in std_logic_vector(5*SYS_W -1 downto 0); -- Dynamically loadable delay tap value for input delay
253  in_delay_tap_out : out std_logic_vector(5*SYS_W -1 downto 0); -- Delay tap value for monitoring input delay
254  delay_locked : out std_logic; -- Locked signal from IDELAYCTRL
255  ref_clock : in std_logic; -- Reference Clock for IDELAYCTRL. Has to come from BUFG.
256 
257 -- Clock and reset signals
258  clk_in : in std_logic; -- Fast clock from PLL/MMCM
259  io_reset : in std_logic); -- Reset signal for IO circuit
260  end component;
261 
262 
263 -- COMPONENT ila_inputRam
264 
265 --PORT (
266 -- clk : IN STD_LOGIC;
267 
268 
269 
270 -- probe0 : IN STD_LOGIC_VECTOR(19 DOWNTO 0)
271 --);
272 --END COMPONENT ;
273 
274 -- signals for ports
275 
276 --in
277  signal q_clk_gtrefclk_pad_n_in : std_logic_vector (19 downto 0);
278  signal q_clk_gtrefclk_pad_p_in : std_logic_vector (19 downto 0);
279  signal rxn_IN : std_logic_vector (79 downto 0);
280  signal rxp_IN : std_logic_vector (79 downto 0);
281  signal ttc_inform_p : std_logic_vector(3 downto 0);
282  signal ttc_inform_n : std_logic_vector(3 downto 0);
283  signal ttc_info : std_logic_vector(37 downto 0);
284  signal ttc_parity : std_logic;
285  signal ctrl_TOB_ready_in : std_logic;
286  signal ctrl_RAW_ready_in : std_logic;
287  signal data_from_fpga_A_p : std_logic_vector(32 downto 0);
288  signal data_from_fpga_A_n : std_logic_vector(32 downto 0);
289  signal data_from_fpga_B_p : std_logic_vector(32 downto 0);
290  signal data_from_fpga_B_n : std_logic_vector(32 downto 0);
291  signal data_from_fpga_C_p : std_logic_vector(32 downto 0);
292  signal data_from_fpga_C_n : std_logic_vector(32 downto 0);
293 
294 --out
295  signal txn_OUT : std_logic_vector (77 downto 0);
296  signal txp_OUT : std_logic_vector (77 downto 0);
297  signal data_to_fpga_X_p : std_logic_vector(32 downto 0);
298  signal data_to_fpga_X_n : std_logic_vector(32 downto 0);
299  signal data_to_fpga_Y_p : std_logic_vector(32 downto 0);
300  signal data_to_fpga_Y_n : std_logic_vector(32 downto 0);
301  signal busy_raw : std_logic;
302  signal busy_tob : std_logic;
303  signal MGT_QUAD_ENABLE : std_logic_vector(19 downto 0) := x"fffff";
304  signal MGT_USE_OTHER_CLK : std_logic_vector(19 downto 0) := x"00000";
305  signal MGT_TX_POWER : std_logic_vector(79 downto 0) := (others => '1');
306  signal MGT_RX_POWER : std_logic_vector(79 downto 0) := (others => '1');
307 
308 -----ipb signal declaration
309  signal clk200, clk_load, ipb_clk, mac_clk, clk40, clk40_rdout_i, clk280, clk280_90, clk200_iodelay : std_logic;
310  signal onehz, ipb_rst, rst_macclk, rst_ipb, start, reset, locked_40m_i : std_logic;
311  signal algo_ipb_in : ipb_rbus; -- this goes to ip_out slave
312  signal algo_ipb_out : ipb_wbus; -- this goes to ip_in slave
313 
314  signal ipbw : ipb_wbus_array(N_SLAVES-1 downto 0);
315  signal ipbr : ipb_rbus_array(N_SLAVES-1 downto 0);
316  signal ipb_in : ipb_rbus;
317  signal ipb_out : ipb_wbus;
318 
319 -----------------mgt signal declaration
320  signal MGT_Commadet_int, rxdata, clk280_int : std_logic_vector (79 downto 0); -- was using n_channels
321 
322 
323 --------------- inter FPGA, control and spi flash signal declaration---------------------------------------------
324  signal flash_clk : std_logic;
325 
326  signal Module_ID, fpga_id, hw_position, fw_rev, fw_tag, datafmt_rev, status : std_logic_vector(31 downto 0);
327  signal trigger_reconfig, reconfig : std_logic;
328 
329  signal control_reg, reconfig_reg : std_logic_vector (31 downto 0);
330  signal master_rx_data_int, master_tx_data_int : std_logic_vector (9 downto 0);
331  signal master_tx_pause_int : std_logic;
332  signal force_rx_error_buf : std_logic_vector(1 downto 0) := (Others => '0');
333 
334  signal data_from_fpga_A, data_from_fpga_B, data_from_fpga_C : std_logic_vector(32 downto 0);
335 
336 
337 
338 ------- agorithm signal declaration
339  signal eg_tob_0, eg_tob_1, eg_tob_2, eg_tob_3, eg_tob_4, eg_tob_5, eg_tob_6, eg_tob_7 : std_logic_vector(31 downto 0);
340  signal OUT_tau_XTOB, OUT_eg_XTOB : AlgoXOutput; -- array 8 x 32b words
341  signal sorted_tau_TOB, sorted_eg_TOB : AlgoTriggerObject; -- 32b word
342  signal OUT_eg_Sync, OUT_tau_Sync : std_logic;
343  signal OUT_eg_Valid, OUT_tau_Valid : std_logic_vector(OUTPUT_TOBS-1 downto 0);
344  signal sorted_eg_Valid, sorted_tau_start, sorted_eg_start : std_logic;
345  signal tau_tob_0, tau_tob_1, tau_tob_2, tau_tob_3, tau_tob_4, tau_tob_5, tau_tob_6, tau_tob_7 : std_logic_vector(31 downto 0);
346 
347  -- merger signlas. Defaults values are needed in case fpgas have no merging module
348  signal data_merge_1, data_merge_2, data_merge_3, data_merge_4 : std_logic_vector(32 downto 0);
349  signal data_merge_i, data_merge_ii : AlgoTriggerObjects(3 downto 0) := (others => (others => '0'));
350  signal sorted_merged_Start, sorted_merged_Valid : std_logic := '0';
351  signal sorted_merged_TOB : AlgoTriggerObject := (others => '0');
352 
353 --- internal rx_data declaration
354 
355 --------------mgt signal declaration
356  signal MGT_CLK_GTREFCLK_PAD_N_IN, MGT_CLK_GTREFCLK_PAD_P_IN, mgt_RXUSRCLK_OUT, rx_resetdone : std_logic_vector(79 downto 0);
357  signal mgt_SOFT_RESET_TX_IN, mgt_SOFT_RESET_RX_IN : std_logic_vector(19 downto 0);
358  signal tx_resetdone, mgt_TXUSRCLK_OUT : std_logic_vector(79 downto 0);
359  signal mgt_sel_tx_clk : std_logic_vector(11 downto 0);
360 
361  signal MGT_RXN_IN, MGT_RXP_IN : mgt_rx_array (19 downto 0);
362 
363  signal MGT_TXN_IN, MGT_TXP_IN : mgt_tx_array(19 downto 0);
364  signal rxdata_quad_array : mgt_rxdata_array (19 downto 0);
365  signal mgt_txdata : mgt_txdata_array(19 downto 0);
366 
367  signal mgt_DATA_VALID_IN : std_logic_vector(79 downto 0);
368  signal mgt_loopback_in : mgt_loopback_array (19 downto 0);
369 
370  signal mgt_rxchariscomma : mgt_rxchariskcomm_array(19 downto 0);
371  signal mgt_rxcharisk : mgt_rxcharisk_array(19 downto 0);
372 
373  signal mgt_rxdisperr : mgt_rxdisperr_array(79 downto 0);
374  signal mgt_rxnotintable : mgt_rxnotintable_array(79 downto 0);
375 
376  signal disperr_error_i, notable_error_i : std_logic_vector(79 downto 0);
377  --signal mgt_rx_fsm_resetdone : std_logic_vector(n_channels-1 downto 0);
378  signal mgt_rx_fsm_resetdone : std_logic_vector(79 downto 0);
379  signal mgt_tx_fsm_resetdone, qpll_fsm_reset_done : std_logic_vector(79 downto 0);
380 
381  signal mgt_QPLLLOCK_OUT, mgt_QPLLREFCLKLOST_OUT : std_logic_vector(19 downto 0);
382 
383  signal gt_rxpd : mgt_rxpd_array(19 downto 0);
384  signal gt_txpd : mgt_txpd_array(19 downto 0);
385 
386  signal mgt_commdet : std_logic_vector(0 downto 0);
387  signal tx_bufstatus : std_logic_vector (159 downto 0);
388  signal rx_realign, error_counter_reset : std_logic_vector (79 downto 0);
389 
390  signal mgt_loopback_reg : std_logic_vector (59 downto 0);
391  signal mgt_txbufstatus : mgt_txbufstatus_array(19 downto 0);
392  signal mgt_rxcommadet : mgt_rxcommadet_array (19 downto 0);
393  signal mgt_rxbyterealign : mgt_rxbyterealign_array(19 downto 0);
394  signal mgt_rx_resetdone : mgt_rxresetdone_array (19 downto 0);
395  signal mgt_rxbyteisaligned : mgt_rxbyteisaligned_array (19 downto 0);
396  signal mgt_tx_resetdone : mgt_txresetdone_array (19 downto 0);
397  signal mgt_txcharisk : mgt_txcharisk_array (19 downto 0);
398 
399  signal rx_disperr_reg, encode_error_reg, mgt_DATA_VALID_IN_reg, rxbyteisaligned, rxdata_out : std_logic_vector (79 downto 0);
400  signal rx_disperr, txcharisk, encode_error, mgt_rxcharisk_reg : std_logic_vector (319 downto 0);
401  signal data_readout_0, data_readout_1, data_readout_2, data_readout_3 : std_logic_vector(223 downto 0);
402 
403  signal bcn_cntr : std_logic_vector(11 downto 0);
404  signal enable_mgt, bcn_synch, crc_error_chan : std_logic_vector(79 downto 0);
405  signal sorted_tau_Valid : std_logic;
406  signal start_pulse_rst : std_logic;
407  signal BC_Reg_sel, mux_sel : std_logic_vector(319 downto 0);
408  -- debug signals
409  signal reg224_latch, ttc_pipe, delay_latch : std_logic_vector(63 downto 0);
410  signal delay_num : std_logic_vector(319 downto 0);
411  signal reg224_latch_0, reg224_latch_1, reg224_latch_2, reg224_latch_3, rx_realign_0, rx_realign_1, rx_realign_2, rx_realign_3 : std_logic;
412  signal delay_latch_0, delay_latch_1, delay_latch_2, delay_latch_3, rx_resetdone_quad111 : std_logic;
413  signal delay_num_0, delay_num_1, delay_num_2, delay_num_3, rx_disperr_0, rx_disperr_1, rx_disperr_2, rx_disperr_3 : std_logic_vector(3 downto 0);
414  signal encode_error_0, encode_error_1, encode_error_2, encode_error_3 : std_logic_vector(3 downto 0);
415  signal bc_cntr_0, bc_cntr_1, bc_cntr_2, bc_cntr_3, bc_mux_cntr_0, bc_mux_cntr_1, bc_mux_cntr_2, bc_mux_cntr_3 : std_logic_vector(139 downto 0);
416 
417 -- signal resetbc_cntr : std_logic;
418  signal bcn_ref : std_logic_vector(4 downto 0);
419 
420  signal pseudo_orbit : std_logic;
421  -- data paths tx phase calibration
422  signal comma_0, comma_1, comma_2, comma_3, data_eq0, data_eq1, data_eq2, data_eq3 : std_logic;
423  signal data_out_0, data_out_1, data_out_2, data_out_3, phase_mux_i : std_logic_vector(31 downto 0);
424  signal test_data : std_logic_vector(33 downto 0);
425  signal rx_data_0, rx_data_1, rx_data_2, rx_data_3, rx_data_4, rx_data_5, rx_data_6, rx_data_7 : mgt_data;
426  signal txdatai_0, txdatai_1, txdatai_2, txdatai_3, txdatai_4, txdatai_5, txdatai_6, txdatai_7, txdatai_8, txdatai_9, txdatai_10, txdatai_11 : std_logic_vector (33 downto 0);
427  signal phase_mux : std_logic_vector(319 downto 0);
428  signal sorted_eg_TOB_i_gt0, sorted_eg_TOB_i_gt1, sorted_eg_TOB_i_gt2, sorted_eg_TOB_i_gt3 : std_logic_vector (33 downto 0);
429  signal sorted_eg_TOB_i_gt4, sorted_eg_TOB_i_gt5, sorted_eg_TOB_i_gt6, sorted_eg_TOB_i_gt7 : std_logic_vector (33 downto 0);
430  signal error_count_0, error_count_1, error_count_2, error_count_3, error_count_i, error_count_i_0 : unsigned(31 downto 0);
431  signal error_count_4, error_count_5, error_count_6, error_count_7 : unsigned(31 downto 0);
432  signal clear_error, comma_detect_ILA : std_logic;
433  signal error_counter : std_logic_vector(1279 downto 0);
434 
435  attribute PRESERVE_SIGNAL : boolean;
436  signal Q210_SOFT_RESET_TX_IN_i, Q210_gt0_txresetdone_i, Q210_GT0_TX_FSM_RESET_DONE_i, Q210_GT0_RX_FSM_RESET_DONE_i : std_logic;
437  signal Q210_GT1_TX_FSM_RESET_DONE_i, Q210_GT1_RX_FSM_RESET_DONE_i, Q210_gt1_txresetdone_i, Q210_gt0_cplllock_i, Q210_gt1_cplllock_i : std_logic;
438  signal Q210_gt0_txcharisk, Q210_gt1_txcharisk, mgt210_tx_bufstatus_i : std_logic_vector(3 downto 0);
439  signal gt0_cpllfbclklost_i, gt1_cpllfbclklost_i : std_logic;
440  signal mgt210_tx_resetdone_i, mgt210_tx_fsm_resetdone_i, mgt210_txclk_i : std_logic_vector (1 downto 0);
441 
442  signal T_TOB_32b_in_i : AlgoTriggerObject; -- 32b owrd
443  signal T_TOB_sync_in_i : std_logic;
444  signal T_TOB_wr_in_i : std_logic;
445  signal TOB_BCN_sync, TOB_BCN_sync_i, TOB_BCN_sync_tau_i, TOB_BCN_sync_eg_i : std_logic;
446  signal TOB_BCN_sync_ii : std_logic;
447  signal data_merge_BCN_A_i, data_merge_BCN_B_i, data_merge_BCN_C_i : std_logic;
448  signal data_merge_BCN_A_ii, data_merge_BCN_B_ii, data_merge_BCN_C_ii : std_logic;
449 
450  signal data_to_X_i, data_to_Y_i : std_logic_vector(32 downto 0);
451 
452 --- Readout signals
453 
454  signal arr_raw_data_in_i : RAW_data_227_type;
455  signal TOPO_TOB_out_char : std_logic;
456  signal TOPO_TOB_out : std_logic_vector(31 downto 0);
457  signal RAW_Data_out_char : std_logic;
458  signal RAW_Data_out : std_logic_vector(31 downto 0);
459  signal sorted_eg_TOB_1, sorted_tau_TOB_1 : std_logic_vector(32 downto 0);
460  signal tob_eg_in : std_logic_vector(511 downto 0);
461  signal tob_tau_in : std_logic_vector(511 downto 0);
462  signal TOB_TXOUTCLK_i, RAW_TXOUTCLK_i : std_logic;
463  signal ttc_inform : std_logic_vector (3 downto 0);
464  signal ECRID_i : std_logic_vector (7 downto 0);
465  signal L1ID_i : std_logic_vector (23 downto 0);
466  signal L1A_i, BCR_i, ECR_i, TTC_parity_i : std_logic;
467  signal privilege_read_i : std_logic; -- privilege read
468  signal ctrl_RAW_ready_i : std_logic;
469  signal ctrl_TOB_ready_i : std_logic;
470  signal sorted_TOB_BCN, sorted_TOB_BCN_i, sorted_TOB_BCN_ii, OUT_TOB_BCN_i : std_logic_vector (11 downto 0); -- sorted TOB BC_ID with delay through ALGO/sorting block
471  signal merged_TOB_BCN_i : std_logic_vector (11 downto 0); -- merged TOB BC_ID with delay through ALGO/merging block
472  signal OUT_XTOB_BCN_i : std_logic_vector (11 downto 0); -- sorted XTOB BC_ID with delay through ALGO/sorting block
473 
474  signal reset_tmp : std_logic;
475 
476 ----------------------------------------------------------------------------------------------------------------------------------------------------------------
477 -- MGT selector signals
478 ------------------------------------------------------------------------------------------------------------------------------------
479 
480  signal mgt_sel_BC_Reg_sel : std_logic_vector(255 downto 0);
481  signal mgt_sel_mux_sel : std_logic_vector(255 downto 0);
482  signal mgt_sel_delay_num : std_logic_vector(255 downto 0);
483  signal mgt_sel_bc_cntr_0 : std_logic_vector(111 downto 0);
484  signal mgt_sel_bc_cntr_1 : std_logic_vector(111 downto 0);
485  signal mgt_sel_bc_cntr_2 : std_logic_vector(111 downto 0);
486  signal mgt_sel_bc_cntr_3 : std_logic_vector(111 downto 0);
487  signal mgt_sel_bc_mux_cntr_0 : std_logic_vector(111 downto 0);
488  signal mgt_sel_bc_mux_cntr_1 : std_logic_vector(111 downto 0);
489  signal mgt_sel_bc_mux_cntr_2 : std_logic_vector(111 downto 0);
490  signal mgt_sel_bc_mux_cntr_3 : std_logic_vector(111 downto 0);
491  signal mgt_sel_RXUSRCLK_OUT : std_logic_vector(63 downto 0);
492  signal mgt_sel_enable_mgt : std_logic_vector(63 downto 0);
493  signal mgt_sel_bcn_synch : std_logic_vector(63 downto 0);
494  signal mgt_sel_crc_error_chan : std_logic_vector(63 downto 0);
495  signal mgt_sel_disperr_error : std_logic_vector(63 downto 0);
496  signal mgt_sel_notable_error : std_logic_vector(63 downto 0);
497  signal mgt_sel_rx_resetdone : std_logic_vector(63 downto 0);
498  signal mgt_sel_Commadet : std_logic_vector(63 downto 0);
499  signal mgt_sel_Data : mgt_rxdata_array (15 downto 0);
500 
501  -- playback ram signals
502  signal kchar_mgt : std_logic_vector(79 downto 0);
503  signal align_frame_mgt : std_logic_vector(79 downto 0);
504 
505  signal rxdata_mgt0 : std_logic_vector(639 downto 0);
506  signal ram_data_mgt0 : std_logic_vector(4559 downto 0);
507  signal rxdata_mgt1 : std_logic_vector(639 downto 0);
508  signal ram_data_mgt1 : std_logic_vector(4559 downto 0);
509  signal rxdata_mgt2 : std_logic_vector(639 downto 0);
510  signal ram_data_mgt2 : std_logic_vector(4559 downto 0);
511  signal rxdata_mgt3 : std_logic_vector(639 downto 0);
512  signal ram_data_mgt3 : std_logic_vector(4559 downto 0);
513 
514  signal mgt_sel_rxdata_mgt0 : std_logic_vector(511 downto 0);
515  signal mgt_sel_rxdata_mgt1 : std_logic_vector(511 downto 0);
516  signal mgt_sel_rxdata_mgt2 : std_logic_vector(511 downto 0);
517  signal mgt_sel_rxdata_mgt3 : std_logic_vector(511 downto 0);
518 
519  signal mgt_sel_ram_data_mgt0 : std_logic_vector(3647 downto 0);
520  signal mgt_sel_ram_data_mgt1 : std_logic_vector(3647 downto 0);
521  signal mgt_sel_ram_data_mgt2 : std_logic_vector(3647 downto 0);
522  signal mgt_sel_ram_data_mgt3 : std_logic_vector(3647 downto 0);
523 
524  signal mgt_sel_kchar : std_logic_vector(63 downto 0);
525  signal mgt_sel_align_frame : std_logic_vector(63 downto 0);
526  signal fpga_number : integer;
527 
528  signal sorted_Start_sel, sorted_Start_sel_1, sorted_Start_sel_i, sorted_Start_sel_ii : std_logic := '0';
529  signal sorted_Valid_sel, sorted_Valid_sel_1, sorted_Valid_sel_i : std_logic := '0';
530  signal sorted_TOB_sel : std_logic_vector (31 downto 0) := (others => '0');
531  signal TOB_BCN_sync_reg_i : std_logic_vector (31 downto 0) := (others => '0');
532  signal sorted_synch_int : std_logic;
533  signal sel_bcn_or_bc_cnt_i : std_logic;
534  signal tob_bc_reg, tob_bc_status : std_logic_vector (31 downto 0);
535  signal TOB_BCN_sync_internal : std_logic;
536  signal dummy1, dummy2, dummy3 : std_logic_vector(74 downto 0);
537  signal tob_delay_reg, tob_delay_status : std_logic_vector (31 downto 0);
538 
539  signal VAUXP_i, VAUXN_i, Vp_i, Vn_i : std_logic;
540 
541  signal golden: std_logic;
542  signal readout_en, mgt_en, data_path_en, input_ram_en, output_rams_en, merge_en, sort_in_ram_en, sort_out_ram_en : std_logic;
543  signal energy_encoding : std_logic_vector( 1 downto 0);
544  signal dynamic_mapping : std_logic;
545  signal bcmuxvalue_sych_reg_i,ttc_orbit_length_reg_i: std_logic_vector (31 downto 0);
546 
547  signal probe0 : STD_LOGIC_VECTOR(34 DOWNTO 0);
548 
549  signal latency_check_in : STD_LOGIC;
550  signal latency_check_out : STD_LOGIC;
551 
552 -- ####### Mark signals ########
553  attribute keep : string;
554  attribute max_fanout : integer;
555  attribute keep of data_merge_i : signal is "true";
556  attribute keep of sorted_eg_TOB : signal is "true";
557  attribute keep of sorted_tau_TOB : signal is "true";
558  attribute keep of sorted_eg_TOB_1 : signal is "true";
559  attribute keep of reset : signal is "true" ;
560 
561  attribute ASYNC_REG : string;
562  attribute ASYNC_REG of force_rx_error_buf : signal is "TRUE";
563 
564 -- #######################################
565 
566 begin
567 
568 
569 -- Port assignments
570 
571  P_RECORD_TO_PORTS (
572  record_in => efex_in,
573  record_out => efex_out,
574  q_clk_gtrefclk_pad_n_in => q_clk_gtrefclk_pad_n_in,
575  q_clk_gtrefclk_pad_p_in => q_clk_gtrefclk_pad_p_in,
576  rxn_IN => rxn_IN,
577  rxp_IN => rxp_IN,
578  ttc_inform_p => ttc_inform_p,
579  ttc_inform_n => ttc_inform_n,
580  ttc_info => ttc_info,
581  ttc_parity => ttc_parity,
582  ctrl_TOB_ready_in => ctrl_TOB_ready_in,
583  ctrl_RAW_ready_in => ctrl_RAW_ready_in,
584  data_from_fpga_A_p => data_from_fpga_A_p,
585  data_from_fpga_A_n => data_from_fpga_A_n,
586  data_from_fpga_B_p => data_from_fpga_B_p,
587  data_from_fpga_B_n => data_from_fpga_B_n,
588  data_from_fpga_C_p => data_from_fpga_C_p,
589  data_from_fpga_C_n => data_from_fpga_C_n,
590  txn_OUT => txn_OUT,
591  txp_OUT => txp_OUT,
592  data_to_fpga_X_p => data_to_fpga_X_p,
593  data_to_fpga_X_n => data_to_fpga_X_n,
594  data_to_fpga_Y_p => data_to_fpga_Y_p,
595  data_to_fpga_Y_n => data_to_fpga_Y_n,
596  busy_raw => busy_raw,
597  busy_tob => busy_tob
598  );
599 
600  fpga_number <= FLAVOUR;
601 
602  reset_tmp <= not locked_40m_i;
603  mgt_DATA_VALID_IN <= (others => '1');
604  clear_error <= not control_reg(2);
605  sel_bcn_or_bc_cnt_i <= control_reg(31); -- selects between BC_MUX value and real data BC value
606 
607 
608  reset_bufg : BUFG -- use global routing for RESET to free up routing resources
609  port map (
610  I => reset_tmp,
611  O => reset
612  );
613 
614  ----------debug signal assignment---------------------------------------------
615  reg224_latch_0 <= reg224_latch(0);
616  reg224_latch_1 <= reg224_latch(1);
617  reg224_latch_2 <= reg224_latch(2);
618  reg224_latch_3 <= reg224_latch(3);
619 
620  delay_latch_0 <= delay_latch(0);
621  delay_latch_1 <= delay_latch(1);
622  delay_latch_2 <= delay_latch(2);
623  delay_latch_3 <= delay_latch(3);
624 
625  delay_num_0 <= delay_num (3 downto 0);
626  delay_num_1 <= delay_num (7 downto 4);
627  delay_num_2 <= delay_num (11 downto 8);
628  delay_num_3 <= delay_num (15 downto 12);
629 
630  rx_realign_0 <= rx_realign(0);
631  rx_realign_1 <= rx_realign(1);
632  rx_realign_2 <= rx_realign(2);
633  rx_realign_3 <= rx_realign(3);
634 
635  rx_disperr_0 <= rx_disperr(3 downto 0);
636  rx_disperr_1 <= rx_disperr(7 downto 4);
637  rx_disperr_2 <= rx_disperr(11 downto 8);
638  rx_disperr_3 <= rx_disperr(15 downto 12);
639 
640  encode_error_0 <= encode_error (3 downto 0);
641  encode_error_1 <= encode_error (7 downto 4);
642  encode_error_2 <= encode_error (11 downto 8);
643  encode_error_3 <= encode_error (15 downto 12);
644 
645  ---------------------------------------------------------------------
646 
647  ---- Power control of the MGT
648  -- All the rx side of the mgt are enabled 64 of them
649  -- "00" = power on and "11" = power down
650  ---------------------------------------------------------------------
651 
652  rx_pwr_on_gen : for i in 0 to 19
653  generate
654  gt_rxpd(i).gt0_rxpd <= not F_MGT_RX_POWER(FLAVOUR)(i*4+0) & not F_MGT_RX_POWER(FLAVOUR)(i*4+0);
655  gt_rxpd(i).gt1_rxpd <= not F_MGT_RX_POWER(FLAVOUR)(i*4+1) & not F_MGT_RX_POWER(FLAVOUR)(i*4+1);
656  gt_rxpd(i).gt2_rxpd <= not F_MGT_RX_POWER(FLAVOUR)(i*4+2) & not F_MGT_RX_POWER(FLAVOUR)(i*4+2);
657  gt_rxpd(i).gt3_rxpd <= not F_MGT_RX_POWER(FLAVOUR)(i*4+3) & not F_MGT_RX_POWER(FLAVOUR)(i*4+3);
658  gt_txpd(i).gt0_txpd <= not F_MGT_TX_POWER(FLAVOUR)(i*4+0) & not F_MGT_TX_POWER(FLAVOUR)(i*4+0);
659  gt_txpd(i).gt1_txpd <= not F_MGT_TX_POWER(FLAVOUR)(i*4+1) & not F_MGT_TX_POWER(FLAVOUR)(i*4+1);
660  gt_txpd(i).gt2_txpd <= not F_MGT_TX_POWER(FLAVOUR)(i*4+2) & not F_MGT_TX_POWER(FLAVOUR)(i*4+2);
661  gt_txpd(i).gt3_txpd <= not F_MGT_TX_POWER(FLAVOUR)(i*4+3) & not F_MGT_TX_POWER(FLAVOUR)(i*4+3);
662  end generate;
663 
664 ---------------------------------------------------------------------------------------------------------------------------------
665 
666 golden <= '0' when DATA_PATH_ENABLED and MGT_ENABLED else '1'; -- when 0 is user image, when 1 golden
667 
668 data_path_en <= '1' when DATA_PATH_ENABLED else '0';
669 mgt_en <= '1' when MGT_ENABLED else '0';
670 input_ram_en <= '1' when INPUT_RAM_ENABLED else '0';
671 output_rams_en <= '1' when OUTPUT_RAMS_ENABLED else '0';
672 sort_in_ram_en <= '1' when SORT_IN_RAM_ENABLED else '0';
673 sort_out_ram_en <= '1' when SORT_OUT_RAM_ENABLED else '0';
674 dynamic_mapping <= '1' when EFEX_POSITION = 0 else '0';
675 energy_encoding <= "00" when ENCODING_MODE = 1 else "01" when ENCODING_MODE = 2 else "11";
676 
677 readout_en <= '1' when READOUT_ENABLED else '0';
678 merge_en <= '1' when MERGE_ENABLED and (FLAVOUR = 1 or FLAVOUR = 2) else '0';
679 
680 -- moddule status assignement
681  Module_ID <= (31 => not golden, -- user (1) / golden image (0)
682  30 downto 28 => std_logic_vector(to_unsigned(FLAVOUR, 3)), -- FPGA flavour, 0 for control FPGA
683  27 downto 26 => fpga_geo_addr,
684  25 downto 20 => "000000", -- space for control serial number
685  19 downto 16 => hardware_addr(11 downto 8), -- shelf address
686  15 downto 12 => eFEX_mapping(to_integer(unsigned(hardware_addr(3 downto 0)))), -- slot address
687  11 downto 0 => X"efe" -- module ID
688  );
689 
690  status <= (
691  30 downto 29 => EG_ALGO_VERSION,
692  28 downto 27 => TAU_ALGO_VERSION, -- not 0 means bdt
693  26 => sort_out_ram_en,
694  25 => sort_in_ram_en,
695  24 => output_rams_en,
696  23 => data_path_en,
697  22 => mgt_en,
698  21 => input_ram_en,
699  20 => readout_en,
700  19 => merge_en,
701  18 => dynamic_mapping,
702  17 downto 16 => energy_encoding,
703  15 downto 0 => delay_num_3 & delay_num_2 & delay_num_1 & delay_num_0,
704  others => '0');
705 
706  start <= control_reg(0);
707  trigger_reconfig <= reconfig; -- and locked;
708  reconfig <= control_reg(30); -- if active it will reconfigure the spi flash.
709 
710  U_1 : entity infrastructure_lib.proc_fpgas
711  generic map (IPBUSPORT => F_IPBUS_PORT_N(FLAVOUR))
712  port map (
713  ipb_clk => ipb_clk,
714  mac_clk => mac_clk,
715  rst_ipb => rst_ipb,
716  rst_macclk => rst_macclk,
717  ipb_in => ipb_in,
718  ipb_out => ipb_out,
719  master_rx_data => master_rx_data,
720  force_rx_error => force_rx_error_buf(1),
721  master_tx_pause => master_tx_pause_int,
722  master_tx_data => master_tx_data
723  );
724 
725 -- Disable incoming ethernet traffic if trigger_reconfig armed...
726  force_rx_error: process(mac_clk)
727  begin
728  if rising_edge(mac_clk) then
729  force_rx_error_buf <= force_rx_error_buf(0) & trigger_reconfig;
730  end if;
731  end process;
732 
733  process(mac_clk)
734  begin
735  if rising_edge(mac_clk) then
736  master_tx_pause_int <= master_tx_pause;
737  end if;
738  end process;
739 
740 ------------------------------------------------------------------------------------------------------
741 -- global decoder at the top level.it implements the top xml
742 -----------------------------------------------------------------------------------------------------
743 
744  global_fabric : entity ipbus_lib.ipbus_fabric_sel
745  generic map(NSLV => N_SLAVES, -- defined in ipbus_decode_top_address_table
746  SEL_WIDTH => ipbus_sel_width)
747  port map(
748  ipb_in => ipb_out,
749  ipb_out => ipb_in,
750  sel => ipbus_sel_L1CaloEfexProcessor(ipb_out.ipb_addr),
751  ipb_to_slaves => ipbw,
752  ipb_from_slaves => ipbr
753  );
754 
755 ---------------------------------------------------------------------------------
756 ----- common id registers slave
757 ---------------------------------------------------------------------------------------
758 
759  common_ID : entity infrastructure_lib.common_id_registers
760  port map (
761  ipb_clk => ipb_clk,
762  ipb_rst => rst_ipb,
763  ipb_in => ipbw(N_SLV_COMMON_ID_VERSION),
764  ipb_out => ipbr(N_SLV_COMMON_ID_VERSION),
765  Module_ID => Module_ID,
766  xml_version => XML_VER,
767  xml_Gitsha => XML_SHA,
768  build_date => GLOBAL_DATE,
769  build_time => GLOBAL_TIME,
770  fw_version => GLOBAL_VER,
771  fw_Gitsha => GLOBAL_SHA
772  );
773 
774 -------------------------------------------------------------------------------------------------------------------
775 ---library versions slave
776 --------------------------------------------------------------------------------------------------------------------
777 
778  library_reg : entity infrastructure_lib.lib_registers
779  port map (
780  ipb_clk => ipb_clk,
781  ipb_rst => rst_ipb,
782  ipb_in => ipbw(N_SLV_EFEX_LIB_VERSION),
783  ipb_out => ipbr(N_SLV_EFEX_LIB_VERSION),
784  constraints_version => CON_VER,
785  constraints_gitsha => CON_SHA,
786  hog_gitsha => HOG_SHA,
787  hog_version => HOG_VER,
788  top_version => TOP_VER,
789  top_gitsha => TOP_SHA,
790  infra_version => INFRASTRUCTURE_LIB_VER,
791  infra_gitsha => INFRASTRUCTURE_LIB_SHA,
792  algo_version => ALGOLIB_VER,
793  algo_gitsha => ALGOLIB_SHA,
794  readout_version => TOB_RDOUT_LIB_VER,
795  readout_gitsha => TOB_RDOUT_LIB_SHA,
796  ipbus_gitsha => IPBUS_LIB_SHA
797  );
798 
799  ----------------------------------------------------------------------------------------------------------------------
800  -- ipbus slaves live in the entity below, and can expose top-level ports and the ipbus fabric is instantiated with in.
801  ----------------------------------------------------------------------------------------------------------------------
802  vp_i <= '0' when flavour = 1 or flavour = 2 else vp;
803  vn_i <= '0' when flavour = 1 or flavour = 2 else vn;
804 
805  VAUXP_i <= '0' when flavour = 1 or flavour = 2 else VAUXP;
806  VAUXN_i <= '0' when flavour = 1 or flavour = 2 else VAUXN;
807 
808  slaves : entity infrastructure_lib.slaves
809  generic map (FPGA_FLAVOUR => FLAVOUR,
810  reg48 => xadc_reg48(FLAVOUR),
811  reg49 => xadc_reg49(FLAVOUR)
812  )
813  port map(
814  ipb_clk => ipb_clk,
815  ipb_rst => rst_ipb,
816  ipb_in => ipbw(N_SLV_COMMON_INFRA),
817  ipb_out => ipbr(N_SLV_COMMON_INFRA),
818  VAUXP => VAUXP_i,
819  VAUXN => VAUXN_i,
820  Vp => Vp_i,
821  Vn => Vn_i,
822  status => status,
823  control_reg => control_reg,
824  tob_delay_reg => tob_delay_reg,
825  tob_delay_status => tob_delay_status,
826  tob_bc_reg => tob_bc_reg,
827  tob_bc_status => tob_bc_status,
828  TOB_BCN_sych_reg => TOB_BCN_sync_reg_i,
829  reconfig_reg => reconfig_reg,
830  bcmuxvalue_sych_reg => bcmuxvalue_sych_reg_i,
831  ttc_orbit_length_reg => ttc_orbit_length_reg_i,
832  flash_miso => flash_miso,
833  flash_le => flash_csn,
834  flash_clko => flash_clk,
835  flash_mosi => flash_mosi
836  );
837 
838 
839 
840 
841 -------------------------------------------------------------
842 -- reconfiguring the spi flash and FPGA logic
843 -------------------------------------------------------------
844  cclk_o : entity infrastructure_lib.startup
845  port map(
846  flash_cclk => flash_clk
847 
848  );
849 
850 
851  configure : entity infrastructure_lib.self_configure
852  port map(
853  clk => ipb_clk, --icap_clk,
854  reset => rst_ipb,
855  WBSTAR => reconfig_reg,
856  trigger => trigger_reconfig,
857  indicator => flash_led
858  );
859 
860 
861 --------------------------------------------------------------------------
862 --- impelemtation of all the clocks required for the design
863 ---------------------------------------------------------------------
864  clock_resources : entity infrastructure_lib.clk_resources
865 
866  port map (
867  gt_clk_p => gt_clk125_p, -- input clock of 125MHz for ipbus
868  gt_clk_n => gt_clk125_n, -- clock 125MHz for ipbus
869  TTC_clk_p => ttc_clk_p, -- TTC clock of 40MHz
870  TTC_clk_n => ttc_clk_n, -- TTC clock of 40MHz
871  reset_clk125 => reset_clk125, -- Reset signal for 125 MHz clock coming from Control FPGA
872  ipb_clk => ipb_clk, -- clock 31.25MHz for ipbus
873  mac_clk => mac_clk, -- clock 125MHz for ipbus
874  clk280 => clk280,
875  clk200 => clk200, -- clock 200MHz for algo
876  clk40 => clk40, -- clock of 40MHz
877  clk40_rdout => clk40_rdout_i, -- clock of 160MHz for readout
878  reset => control_reg(3), -- to reset the mmcm of the 280M fabric clock
879  onehz => onehz,
880  rst_macclk => rst_macclk, -- internal reset for the ipbus logic
881  rst_ipb => rst_ipb,
882  locked_40m => locked_40m_i, -- lock signal for 40MH clock
883  load => clk_load, --clk 40MHz, 20% duty cycle, -36 deg phase
884  clk200_iodelay => clk200_iodelay -- pure 200 MHz clock for the IODELAY
885  );
886 
887 -- This selects sorted TOBs for FPGA 1 OR 2
888  clk_proc : process (clk280)
889  begin
890  if clk280'event and clk280 = '1' then
891  T_TOB_32b_in_i <= sorted_merged_TOB; -- 32b
892  T_TOB_sync_in_i <= sorted_merged_Start; -- 1b
893  T_TOB_wr_in_i <= sorted_merged_Valid; -- 1b
894  OUT_TOB_BCN_i <= merged_TOB_BCN_i; -- 1b
895  end if;
896  end process;
897 
898  ----------------------------------------------------
899  -- ttc information signals
900  ----------------------------------------------------
901  input_f5_to_f1 : for i in 0 to 3 generate
902 
903  f5_to_f1 : IBUFDS
904  port map(
905  i => ttc_inform_p (i),
906  ib => ttc_inform_n (i),
907  o => ttc_inform(i)
908  );
909  end generate;
910 
911 
912  synch_L1A_in : process (clk40) -- synch L1A_in with 40MHz
913  begin
914  if clk40'event and clk40 = '0' then -- sample on FALLING EDGE clock
915  L1A_i <= ttc_inform(0); -- this is L1A from TTC
916  BCR_i <= ttc_inform(1); -- this is BCR from TTC
917  ECR_i <= ttc_inform(2); -- this is ECR from TTC
918  privilege_read_i <= ttc_inform(3); -- this is Privilege Read from TTC
919  ECRID_i <= ttc_info(31 downto 24); -- this is ECRID from TTC
920  L1ID_i <= ttc_info(23 downto 0); -- this is L1ID from TTC
921  ttc_parity_i <= ttc_parity; -- this is odd parity over ECRID and L1ID
922  end if;
923  end process;
924 
925 -----------------------------------------------------------------------------
926 --- TOB read out
927 ------------------------------------------------------------------------------
928  READOUT_IF : if (READOUT_ENABLED) generate
929  Readout_block : entity TOB_rdout_lib.Readout_logic_top
930  generic map (FPGA_NUMBER => FLAVOUR)
931  port map(
932  RST => reset,
933  hw_addr => fpga_geo_addr, -- FPGA Hardware Address
934  ipb_rst => rst_ipb,
935  ipb_clk => ipb_clk,
936  IPb_in => ipbw(N_SLV_EFEX_READOUT), -- The signals going from master to slaves
937  IPb_out => ipbr(N_SLV_EFEX_READOUT), -- The signals going from slaves to master
938  clk_load_in => clk_load, -- 40Mhz input signal at 20% duty cycle
939  clk_40M_rdout => clk40_rdout_i, -- 40MHz to only Readout resets only
940  clk_200M_in => clk200,
941  clk_280M_in => clk280,
942  clk_40M_in => clk40,
943  shelf_number => Module_ID(19 downto 16), -- shelf address
944  efex_slot_num => Module_ID(15 downto 12), -- slot address
945  TOB_TXOUTCLK => TOB_TXOUTCLK_i,
946  RAW_TXOUTCLK => RAW_TXOUTCLK_i,
947  -- eXtended TOB data readout signals
948  XTOB_eg_in => OUT_eg_XTOB, -- array 8 * 64b of XTOBs e/g
949  XTOB_eg_Valid_flg_in => OUT_eg_Valid, -- 8b XTOB e/g has valid data
950  XTOB_eg_sync_in => OUT_eg_Sync, -- XTOB e/g sync signal
951  XTOB_tau_in => OUT_tau_XTOB, -- array 8 * 64b of XTOBs tau
952  XTOB_tau_Valid_flg_in => OUT_tau_Valid, -- 8b XTOB tau has valid data
953  XTOB_tau_sync_in => OUT_tau_Sync, -- XTOB tau sync signal
954  OUT_XTOB_BCN => OUT_XTOB_BCN_i(6 downto 0), -- sorted XTOB BC_ID with delay through ALGO/sorting block
955  -- sorted TOB data readout signals
956  -- F1 reads e/g TOBs and F2 reads tau TOBs
957  -- so same firmware in both FPGAs, use hw addr to differentiate
958  T_TOB_32b_in => T_TOB_32b_in_i, -- sorted TOBs 32b 7 in series
959  T_TOB_sync_in => T_TOB_sync_in_i, -- sorted TOB start signal
960  T_TOB_valid_in => T_TOB_wr_in_i, -- sorted TOB write signal
961  OUT_TOB_BCN => OUT_TOB_BCN_i(6 downto 0), -- sorted TOB BC_ID with delay through ALGO/sorting block
962  -- L1A signal input
963  L1A_in => L1A_i,
964  -- ECR signal input
965  ECR_in => ECR_i,
966  -- BCR signal input
967  BCR_in => BCR_i,
968  TTC_read_all_in => privilege_read_i, -- privilege read in
969  local_BCN_out => bcn_cntr, -- BCN generated in eFEX
970  TTC_L1A_ID_EXT_in => ECRID_i,
971  TTC_L1A_ID_in => L1ID_i,
972  TTC_parity_in => ttc_parity_i,
973  TOB_ready_in => ctrl_TOB_ready_in, -- back pressure from cntl FPGA
974  RAW_ready_in => ctrl_RAW_ready_in, -- back pressure from cntl FPGA
975  busy_raw => busy_raw, -- raw data busy out
976  busy_tob => busy_tob, -- tob data busy out
977  TOB_out_is_char => TOPO_TOB_out_char, -- o/p
978  TOB_out => TOPO_TOB_out, -- o/p sorted TOPO TOBs 32b out to MGT
980 -- link_error_flags_in => (others => (others => '0')), -- i/p array 49 x 4 bit per link
981  mgt_enable_in => ReadoutMGTEnable(FLAVOUR, mgt_sel_enable_mgt),
982  RAW_data_in => arr_raw_data_in_i, -- i/p array 49 x 227b input frames
983  RAW_out_is_char => RAW_Data_out_char, -- o/p RAW data valid 32b out to MGT
984  RAW_data_out => RAW_Data_out -- o/p RAW data 32b out to MGT
985  );
986  end generate;
987  --------------------------------------------------------------------------
988  -- Top TOB merging and sorting Module
989  -----------------------------------------------------------------------------------
990  inter_FPGA_io : for i in 0 to 32 generate
991 
992  this_to_X : OBUFDS
993  port map(
994  o => data_to_fpga_X_p(i),
995  ob => data_to_fpga_X_n(i),
996  i => data_to_X_i(i)
997  );
998 
999  this_to_Y : OBUFDS
1000  port map(
1001  o => data_to_fpga_Y_p(i),
1002  ob => data_to_fpga_Y_n(i),
1003  i => data_to_Y_i(i)
1004  );
1005 
1006  end generate inter_FPGA_io;
1007 
1008  data_to_X_i <= (others => '0') when FLAVOUR = 1 else -- pFPGA 2, 3, 4 send sorted_eg_TOB to pFPGA 1, Bus X
1009  sorted_eg_TOB_1;
1010 
1011  data_to_Y_i <= (others => '0') when FLAVOUR = 2 else -- pFPGA 1, 3, 4 send sorted_tau_TOB to pFPGA 2, Bus Y
1012  sorted_tau_TOB_1;
1013 
1014 
1015  ------------------------------------------------------------
1016  io_reg_0 : process(clk280)
1017  begin
1018  if clk280' event and clk280 = '1' then
1019  if TOB_BCN_sync_reg_i(31) = '1' then
1020  sorted_eg_TOB_1 <= TOB_BCN_sync_eg_i & X"00000" & sorted_TOB_BCN;
1021  else
1022  sorted_eg_TOB_1 <= TOB_BCN_sync_eg_i & sorted_eg_TOB;
1023  end if;
1024  end if;
1025  end process;
1026 
1027  io_reg_1 : process(clk280)
1028  begin
1029  if clk280' event and clk280 = '1' then
1030  if TOB_BCN_sync_reg_i(31) = '1' then
1031  sorted_tau_TOB_1 <= TOB_BCN_sync_tau_i & X"00000" & sorted_TOB_BCN;
1032  else
1033  sorted_tau_TOB_1 <= TOB_BCN_sync_tau_i & sorted_tau_TOB;
1034  end if;
1035  end if;
1036  end process;
1037 
1038 -- Create TOB synchronisation signal
1039  TOB_BCN_sync_proc : process (clk280)
1040  begin
1041  if clk280'event and clk280 = '1' then
1042  if (sorted_TOB_BCN = TOB_BCN_sync_reg_i(11 downto 0)) and (sorted_eg_start = '1') then
1043  TOB_BCN_sync_eg_i <= '1';
1044  else
1045  TOB_BCN_sync_eg_i <= '0';
1046  end if;
1047 
1048  if (sorted_TOB_BCN = TOB_BCN_sync_reg_i(11 downto 0)) and (sorted_tau_start = '1') then
1049  TOB_BCN_sync_tau_i <= '1';
1050  else
1051  TOB_BCN_sync_tau_i <= '0';
1052  end if;
1053 
1054  end if;
1055  end process;
1056 
1057 ----------------------------------------------------
1058 
1059 -- ILA_merging_1 : ila_ipbus_fabric_rd_wr
1060 -- port map (
1061 -- clk => clk280,
1062 -- probe0(31 downto 0) => sorted_eg_TOB_1(31 downto 0), --36b
1063 -- probe0(35 downto 32) => (others => '0'), --36b
1064 -- probe1(31 downto 0) => sorted_tau_TOB_1(31 downto 0), --36b
1065 -- probe1(35 downto 32) => (others => '0'), --36b
1066 -- probe2(0) => sorted_eg_TOB_1(32), -- 1b
1067 -- probe3(0) => sorted_tau_TOB_1(32), -- 1b
1068 -- probe4(0) => L1A_i, -- 1b
1069 -- probe5(0) => sorted_eg_Start, --36b
1070 -- probe5(7 downto 1) => sorted_TOB_BCN_i, --36b
1071 -- probe5(35 downto 8) => (others => '0'), --36b
1072 -- probe6 => (others => '0'), --36b
1073 -- probe7(0) => BCR_i, -- 1b
1074 -- probe8(0) => TOB_BCN_sync_eg_i, -- 1b
1075 -- probe9(0) => TOB_BCN_sync_tau_i -- 1b
1076 -- );
1077 
1078 -- ILA_merging_2 : ila_ipbus_fabric_rd_wr
1079 -- port map (
1080 -- clk => clk280,
1081 -- probe0(6 downto 0) => OUT_XTOB_BCN_i(6 downto 0), --36b
1082 -- probe0(35 downto 7) => (others => '0'), --36b
1083 -- probe1(6 downto 0) => OUT_TOB_BCN_i(6 downto 0), --36b
1084 -- probe1(35 downto 7) => (others => '0'), --36b
1085 -- probe2(0) => sorted_eg_TOB_1(32), -- 1b
1086 -- probe3(0) => sorted_tau_TOB_1(32), -- 1b
1087 -- probe4(0) => L1A_i, -- 1b
1088 -- probe5(0) => sorted_eg_Start, --36b
1089 -- probe5(35 downto 1) => (others => '0'), --36b
1090 -- probe6(11 downto 0) => bcn_cntr, --32b
1091 -- probe6(35 downto 12) => (others => '0'), --32b
1092 -- probe7(0) => BCR_i, -- 1b
1093 -- probe8(0) => TOB_BCN_sync_eg_i, -- 1b
1094 -- probe9(0) => TOB_BCN_sync_tau_i -- 1b
1095 -- );
1096 
1097 -------------------------------------------------------------------------------------------
1098 ------Data Path Block
1099 ------------------------------------------------------------------------------------------
1100 DATA_PATH_IF: if DATA_PATH_ENABLED generate
1101  data_path_Module : entity infrastructure_lib.data_path_block
1102  generic map (ENABLE_INPUT_RAM => INPUT_RAM_ENABLED,
1103  ENABLE_OUTPUT_RAMS => OUTPUT_RAMS_ENABLED,
1104  ENCODING_MODE => ENCODING_MODE,
1105  EFEX_POSITION => EFEX_POSITION,
1106  ENABLE_SORTING_INPUT_RAM => SORT_IN_RAM_ENABLED,
1107  ENABLE_SORTING_OUTPUT_RAM => SORT_OUT_RAM_ENABLED,
1108  FPGA_NUMBER => FLAVOUR,
1109  EG_ALGO_VERSION => EG_ALGO_VERSION,
1110  TAU_ALGO_VERSION => TAU_ALGO_VERSION
1111  )
1112  port map(
1113  clk200 => clk200, -- clk200 genearte fromm the ttc clock of 40MHz
1114  rx_clk280 => mgt_sel_RXUSRCLK_OUT, -- Generated rx clocks of 280MHz from the mgt pll.
1115  clk280 => clk280, -- clk280 genearte fromm the ttc clock of 40MHz
1116  reset => reset, -- reset that is active when the 40MHz MMCM is not locked.
1117  ttc_clk => clk40, -- clk40 genearte fromm the ttc clock of 40MHz
1118  in_Load => clk_load, --load generated by the 40MHz as 40Hz with duty cycle of 20%
1119  enable_mgt => mgt_sel_enable_mgt, -- enable for the rx_data register before the top_synch block.
1120  start => start,
1121  start_pulse_rst => start_pulse_rst,
1122  --IPBus connection
1123  ipb_clk => ipb_clk,
1124  ipb_rst => rst_ipb,
1125  ipb_in_algo => ipbw(N_SLV_EFEX_ALGORITHM),
1126  ipb_out_algo => ipbr(N_SLV_EFEX_ALGORITHM),
1127  ipb_in_sorting => ipbw(N_SLV_EFEX_SORTING),
1128  ipb_out_sorting => ipbr(N_SLV_EFEX_SORTING),
1129  sel_bcn_or_bc_cnt => sel_bcn_or_bc_cnt_i,
1130  pseudo_orbit => pseudo_orbit,
1131  RAW_data => arr_raw_data_in_i, -- change to array of 49 x 227b data words
1132  BC_Reg_sel => mgt_sel_BC_Reg_sel,
1133  BCR_in => BCR_i,
1134  bcmuxvalue_sych_reg => bcmuxvalue_sych_reg_i(11 downto 0),
1135  ttc_orbit_length_reg => ttc_orbit_length_reg_i(11 downto 0),
1136  mux_sel => mgt_sel_mux_sel,
1137  delay_num => mgt_sel_delay_num,
1138  bc_cntr_0 => mgt_sel_bc_cntr_0,
1139  bc_cntr_1 => mgt_sel_bc_cntr_1,
1140  bc_cntr_2 => mgt_sel_bc_cntr_2,
1141  bc_cntr_3 => mgt_sel_bc_cntr_3,
1142  bc_mux_cntr_0 => mgt_sel_bc_mux_cntr_0,
1143  bc_mux_cntr_1 => mgt_sel_bc_mux_cntr_1,
1144  bc_mux_cntr_2 => mgt_sel_bc_mux_cntr_2,
1145  bc_mux_cntr_3 => mgt_sel_bc_mux_cntr_3,
1146  bcn_synch => mgt_sel_bcn_synch,
1147  crc_error_chan => mgt_sel_crc_error_chan,
1148  rx_resetdone => mgt_sel_rx_resetdone,
1149  --debug signal for synch
1150  data_readout_0 => data_readout_0,
1151  data_readout_1 => data_readout_1,
1152  data_readout_2 => data_readout_2,
1153  data_readout_3 => data_readout_3,
1154  Reg224_latch => Reg224_latch,
1155  ttc_pipe => ttc_pipe,
1156  delay_latch => delay_latch,
1157  -- out ports eg
1158  OUT_eg_Sync => OUT_eg_Sync,
1159  OUT_eg_Valid => OUT_eg_Valid,
1160  OUT_eg_XTOB => OUT_eg_XTOB,
1161  OUT_XTOB_BCN => OUT_XTOB_BCN_i,
1162  --
1163  OUT_sorted_eg_TOB => sorted_eg_TOB, -- 32b
1164  OUT_sorted_eg_Sync => sorted_eg_Start, -- 1b
1165  OUT_sorted_eg_Valid => sorted_eg_Valid, -- 1b
1166  OUT_TOB_BCN => sorted_TOB_BCN,
1167 
1168  -- out ports tau
1169  OUT_tau_Sync => OUT_tau_Sync,
1170  OUT_tau_Valid => OUT_tau_Valid,
1171  OUT_tau_XTOB => OUT_tau_XTOB,
1172 
1173  OUT_sorted_tau_TOB => sorted_tau_TOB, -- 32b
1174  OUT_sorted_tau_Sync => sorted_tau_start, -- 1b
1175  OUT_sorted_tau_Valid => sorted_tau_Valid, -- 1b
1176 
1177  -- playback ram
1178  sel_data_in => control_reg(4),
1179  ram_data_mgt0 => mgt_sel_ram_data_mgt0,
1180  ram_data_mgt1 => mgt_sel_ram_data_mgt1,
1181  ram_data_mgt2 => mgt_sel_ram_data_mgt2,
1182  ram_data_mgt3 => mgt_sel_ram_data_mgt3,
1183 
1184  ---- MGT signals rx_data and mgt_commadet signals of all rx channells
1185  MGT_Commadet => mgt_sel_Commadet,
1186  MGT_Data => mgt_sel_Data,
1187  align_frame => mgt_sel_align_frame,
1188  disperr_error => mgt_sel_disperr_error,
1189  notable_error => mgt_sel_notable_error
1190  );
1191 end generate;
1192 
1193 
1194 MGT_IF: if MGT_ENABLED generate
1195 
1196  MGT_SELECTOR_RX (
1197  fpga_number => fpga_number,
1198  in_BC_Reg_sel => BC_Reg_sel,
1199  in_mux_sel => mux_sel,
1200  in_delay_num => delay_num,
1201  in_bc_cntr_0 => bc_cntr_0,
1202  in_bc_cntr_1 => bc_cntr_1,
1203  in_bc_cntr_2 => bc_cntr_2,
1204  in_bc_cntr_3 => bc_cntr_3,
1205  in_bc_mux_cntr_0 => bc_mux_cntr_0,
1206  in_bc_mux_cntr_1 => bc_mux_cntr_1,
1207  in_bc_mux_cntr_2 => bc_mux_cntr_2,
1208  in_bc_mux_cntr_3 => bc_mux_cntr_3,
1209 
1210  in_rxdata_mgt0 => rxdata_mgt0,
1211  in_rxdata_mgt1 => rxdata_mgt1,
1212  in_rxdata_mgt2 => rxdata_mgt2,
1213  in_rxdata_mgt3 => rxdata_mgt3,
1214 
1215  in_ram_data_mgt0 => ram_data_mgt0,
1216  in_ram_data_mgt1 => ram_data_mgt1,
1217  in_ram_data_mgt2 => ram_data_mgt2,
1218  in_ram_data_mgt3 => ram_data_mgt3,
1219 
1220  in_kchar => kchar_mgt,
1221  in_align_frame => align_frame_mgt,
1222 
1223  in_mgt_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT,
1224  in_enable_mgt => enable_mgt,
1225  in_bcn_synch => bcn_synch,
1226  in_crc_error_chan => crc_error_chan,
1227  in_disperr_error => disperr_error_i,
1228  in_notable_error => notable_error_i,
1229 
1230  in_rx_resetdone => rx_resetdone,
1231 
1232  out_BC_Reg_sel => mgt_sel_BC_Reg_sel,
1233  out_mux_sel => mgt_sel_mux_sel,
1234  out_delay_num => mgt_sel_delay_num,
1235  out_bc_cntr_0 => mgt_sel_bc_cntr_0,
1236  out_bc_cntr_1 => mgt_sel_bc_cntr_1,
1237  out_bc_cntr_2 => mgt_sel_bc_cntr_2,
1238  out_bc_cntr_3 => mgt_sel_bc_cntr_3,
1239  out_bc_mux_cntr_0 => mgt_sel_bc_mux_cntr_0,
1240  out_bc_mux_cntr_1 => mgt_sel_bc_mux_cntr_1,
1241  out_bc_mux_cntr_2 => mgt_sel_bc_mux_cntr_2,
1242  out_bc_mux_cntr_3 => mgt_sel_bc_mux_cntr_3,
1243  out_mgt_RXUSRCLK_OUT => mgt_sel_RXUSRCLK_OUT,
1244  out_enable_mgt => mgt_sel_enable_mgt,
1245  out_bcn_synch => mgt_sel_bcn_synch,
1246  out_crc_error_chan => mgt_sel_crc_error_chan,
1247  out_disperr_error => mgt_sel_disperr_error,
1248  out_notable_error => mgt_sel_notable_error,
1249 
1250  out_rxdata_mgt0 => mgt_sel_rxdata_mgt0,
1251  out_rxdata_mgt1 => mgt_sel_rxdata_mgt1,
1252  out_rxdata_mgt2 => mgt_sel_rxdata_mgt2,
1253  out_rxdata_mgt3 => mgt_sel_rxdata_mgt3,
1254 
1255  out_ram_data_mgt0 => mgt_sel_ram_data_mgt0,
1256  out_ram_data_mgt1 => mgt_sel_ram_data_mgt1,
1257  out_ram_data_mgt2 => mgt_sel_ram_data_mgt2,
1258  out_ram_data_mgt3 => mgt_sel_ram_data_mgt3,
1259 
1260  out_kchar => mgt_sel_kchar,
1261  out_rx_resetdone => mgt_sel_rx_resetdone,
1262  out_align_frame => mgt_sel_align_frame,
1263 
1264  in_MGT_Commadet => MGT_Commadet_int,
1265  in_MGT_Data => rxdata_quad_array,
1266 
1267  out_MGT_Commadet => mgt_sel_Commadet,
1268  out_MGT_Data => mgt_sel_Data);
1269 
1270 
1271  MGT_SELECTOR_TX (
1272 
1273  fpga_number => fpga_number,
1274  in_txdata_0 => txdatai_0,
1275  in_txdata_1 => txdatai_1,
1276  in_txdata_2 => txdatai_2,
1277  in_txdata_3 => txdatai_3,
1278  in_txdata_4 => txdatai_4,
1279  in_txdata_5 => txdatai_5,
1280  in_txdata_6 => txdatai_6,
1281  in_txdata_7 => txdatai_7,
1282  in_txdata_8 => txdatai_8,
1283  in_txdata_9 => txdatai_9,
1284  in_txdata_10 => txdatai_10,
1285  in_txdata_11 => txdatai_11,
1286  in_mgt_usr_clk => mgt_TXUSRCLK_OUT,
1287 
1288  in_topo_k => TOPO_TOB_out_char,
1289  in_raw_k => RAW_Data_out_char,
1290  in_topo_data => TOPO_TOB_out,
1291  in_raw_data => RAW_Data_out,
1292 
1293  out_topo_tob_clk => TOB_TXOUTCLK_i,
1294  out_topo_raw_clk => RAW_TXOUTCLK_i,
1295 
1296  out_txcharisk_quad_array => mgt_txcharisk,
1297  out_txdata_quad_array => mgt_txdata,
1298  out_mgt_usr_clk => mgt_sel_tx_clk
1299  );
1300 
1301 -------------------------------------------------------------------------------------------------------------------------------
1302  -- This will use generate statement to assgin the MGT_Commadet_int, mgt_loopback_in,mgt_rxcharisk_reg,rx_realign,rx_disperr,encode_error
1303  -- It will generate the status signals of 16 mgts of tx_rx
1304 --------------------------------------------------------------------------------------------------------------------------------
1305  mgt_gen : for i in 0 to 19 --loop
1306 
1307  generate
1308 
1309  MGT_Commadet_int(0+4*i downto 0+4*i) <= mgt_rxchariscomma(i).gt0_rxchariscomma_out(0 downto 0); -- asginment of the rxchriscomma
1310  MGT_Commadet_int(1+4*i downto 1+4*i) <= mgt_rxchariscomma(i).gt1_rxchariscomma_out(0 downto 0); -- asginment of the rxchriscomma
1311  MGT_Commadet_int(2+4*i downto 2+4*i) <= mgt_rxchariscomma(i).gt2_rxchariscomma_out(0 downto 0); -- asginment of the rxchriscomma
1312  MGT_Commadet_int(3+4*i downto 3+4*i) <= mgt_rxchariscomma(i).gt3_rxchariscomma_out(0 downto 0); -- asginment of the rxchriscomma
1313 
1314  rx_realign(0+4*i) <= mgt_rxbyterealign(i).gt0_rxbyterealign; -- asignment of rxbyterealign
1315  rx_realign(1+4*i) <= mgt_rxbyterealign(i).gt1_rxbyterealign; -- asignment of rxbyterealign
1316  rx_realign(2+4*i) <= mgt_rxbyterealign(i).gt2_rxbyterealign; -- asignment of rxbyterealign
1317  rx_realign(3+4*i) <= mgt_rxbyterealign(i).gt3_rxbyterealign; -- asignment of rxbyterealign
1318 
1319  rx_resetdone(0+4*i) <= mgt_rx_resetdone(i).gt0_rxresetdone; -- asignment of rx_resetdone
1320  rx_resetdone(1+4*i) <= mgt_rx_resetdone(i).gt1_rxresetdone; -- asignment of rx_resetdone
1321  rx_resetdone(2+4*i) <= mgt_rx_resetdone(i).gt2_rxresetdone; -- asignment of rx_resetdone
1322  rx_resetdone(3+4*i) <= mgt_rx_resetdone(i).gt3_rxresetdone; -- asignment of rx_resetdone
1323 
1324  rxbyteisaligned(0+4*i) <= mgt_rxbyteisaligned(i).gt0_rxbyteisaligned;
1325  rxbyteisaligned(1+4*i) <= mgt_rxbyteisaligned(i).gt1_rxbyteisaligned;
1326  rxbyteisaligned(2+4*i) <= mgt_rxbyteisaligned(i).gt2_rxbyteisaligned;
1327  rxbyteisaligned(3+4*i) <= mgt_rxbyteisaligned(i).gt3_rxbyteisaligned;
1328 
1329  mgt_rxcharisk_reg(3+16*i downto 16*i) <= mgt_rxcharisk(i).gt0_rxcharisk_out;
1330  mgt_rxcharisk_reg(7+16*i downto 4+16*i) <= mgt_rxcharisk(i).gt1_rxcharisk_out;
1331  mgt_rxcharisk_reg(11+16*i downto 8+16*i) <= mgt_rxcharisk(i).gt2_rxcharisk_out;
1332  mgt_rxcharisk_reg(15+16*i downto 12+16*i) <= mgt_rxcharisk(i).gt3_rxcharisk_out;
1333 
1334  align_frame_mgt(0+4*i) <= mgt_rxcharisk(i).gt0_rxcharisk_out(1) and mgt_rxcharisk(i).gt0_rxcharisk_out(0);
1335  align_frame_mgt(1+4*i) <= mgt_rxcharisk(i).gt1_rxcharisk_out(1) and mgt_rxcharisk(i).gt1_rxcharisk_out(0);
1336  align_frame_mgt(2+4*i) <= mgt_rxcharisk(i).gt2_rxcharisk_out(1) and mgt_rxcharisk(i).gt2_rxcharisk_out(0);
1337  align_frame_mgt(3+4*i) <= mgt_rxcharisk(i).gt3_rxcharisk_out(1) and mgt_rxcharisk(i).gt3_rxcharisk_out(0);
1338 
1339  rx_disperr(3+16*i downto 16*i) <= mgt_rxdisperr(i).gt0_rxdisperr;
1340  rx_disperr(7+16*i downto 4+16*i) <= mgt_rxdisperr(i).gt1_rxdisperr;
1341  rx_disperr(11+16*i downto 8+16*i) <= mgt_rxdisperr(i).gt2_rxdisperr;
1342  rx_disperr(15+16*i downto 12+16*i) <= mgt_rxdisperr(i).gt3_rxdisperr;
1343 
1344  encode_error(3+16*i downto 16*i) <= mgt_rxnotintable(i).gt0_rxnotintable; -- asignment of 10b/8b encoding error-
1345  encode_error(7+16*i downto 4+16*i) <= mgt_rxnotintable(i).gt1_rxnotintable; -- asignment of 10b/8b encoding error
1346  encode_error(11+16*i downto 8+16*i) <= mgt_rxnotintable(i).gt2_rxnotintable; -- asignment of 10b/8b encoding error
1347  encode_error(15+16*i downto 12+16*i) <= mgt_rxnotintable(i).gt3_rxnotintable; -- asignment of 10b/8b encoding error
1348 
1349  MGT_RXN_IN(i).RXN_IN <= RXN_IN(3+4*i downto 4*i); -- rx input asignment
1350  MGT_RXP_IN(i).RXP_IN <= RXP_IN(3+4*i downto 4*i); -- rx input asignment
1351 
1352  mgt_DATA_VALID_IN(i) <= mgt_DATA_VALID_IN_reg(i);
1353 
1354  end generate mgt_gen;
1355 
1356 ------------------------------------------------------------------------------------------------------------------
1357  -- This will use generate statament in order to assign tx side signals and control loopbackof the MGT_TX quads
1358 ------------------------------------------------------------------------------------------------------------------
1359 
1360  internal_mgt_tx_gen : for i in 0 to 19
1361  generate
1362  tx_resetdone(0+4*i) <= mgt_tx_resetdone(i).gt0_txresetdone;
1363  tx_resetdone(1+4*i) <= mgt_tx_resetdone(i).gt1_txresetdone;
1364  tx_resetdone(2+4*i) <= mgt_tx_resetdone(i).gt2_txresetdone;
1365  tx_resetdone(3+4*i) <= mgt_tx_resetdone(i).gt3_txresetdone;
1366 
1367  txcharisk(03+16*i downto 00+16*i) <= mgt_txcharisk(i).gt0_txcharisk;
1368  txcharisk(07+16*i downto 04+16*i) <= mgt_txcharisk(i).gt1_txcharisk;
1369  txcharisk(11+16*i downto 08+16*i) <= mgt_txcharisk(i).gt2_txcharisk;
1370  txcharisk(15+16*i downto 12+16*i) <= mgt_txcharisk(i).gt3_txcharisk;
1371 
1372  mgt_loopback_in(i).gt0_loopback_in <= mgt_loopback_reg(2+3*i downto 3*i);
1373  end generate;
1374 
1375  external_mgt_tx_gen_1 : for i in 0 to F_MGT_USE_OTHER_CLK_N(FLAVOUR)-1
1376  generate
1377  TXN_OUT(3+4*i downto 4*i) <= MGT_TXN_IN(i).TXN_OUT;
1378  TXP_OUT(3+4*i downto 4*i) <= MGT_TXP_IN(i).TXP_OUT;
1379  end generate;
1380 
1381  TXN_OUT(77 downto 76) <= MGT_TXN_IN(F_MGT_USE_OTHER_CLK_N(FLAVOUR)).TXN_OUT(1 downto 0);
1382  TXP_OUT(77 downto 76) <= MGT_TXP_IN(F_MGT_USE_OTHER_CLK_N(FLAVOUR)).TXP_OUT(1 downto 0);
1383 
1384  external_mgt_tx_gen_2 : for i in F_MGT_USE_OTHER_CLK_N(FLAVOUR)+1 to 19
1385  generate
1386  TXN_OUT(3+4*(i-1) downto 4*(i-1)) <= MGT_TXN_IN(i).TXN_OUT;
1387  TXP_OUT(3+4*(i-1) downto 4*(i-1)) <= MGT_TXP_IN(i).TXP_OUT;
1388  end generate;
1389 
1390 ---------------------------------------------------------------------------------------
1391 ---- signal assignments of the 20 mgts tx_rx
1392 --------------------------------------------------------------------------------------
1393  MGT_TX_RX : entity infrastructure_lib.MGT_4_quad_gen
1394  generic map(QUAD_ENABLE => F_MGT_QUAD_ENABLE(FLAVOUR))
1395  port map (
1396  clk280 => clk280,
1397  TTC_CLK => clk40,
1398  MGT_CLK_GTREFCLK_PAD_N_IN => Q_CLK_GTREFCLK_PAD_N_IN,
1399  MGT_CLK_GTREFCLK_PAD_P_IN => Q_CLK_GTREFCLK_PAD_P_IN,
1400  mgt_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT,
1401  mgt_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT,
1402  mgt_SOFT_RESET_TX_IN => mgt_SOFT_RESET_TX_IN,
1403  mgt_SOFT_RESET_RX_IN => mgt_SOFT_RESET_RX_IN,
1404  -- data
1405  RXN_IN => MGT_RXN_IN,
1406  RXP_IN => MGT_RXP_IN,
1407  TXN_IN => MGT_TXN_IN,
1408  TXP_IN => MGT_TXP_IN,
1409  rxdata_quad_array => rxdata_quad_array,
1410  txdata_quad_array => mgt_txdata,
1411  -- status and monitoring
1412  gt_rxpd_array => gt_rxpd,
1413  gt_txpd_array => gt_txpd,
1414  mgt_DATA_VALID_IN => mgt_DATA_VALID_IN,
1415  mgt_TX_FSM_RESET_DONE => mgt_tx_fsm_resetdone,
1416  mgt_RX_FSM_RESET_DONE => mgt_rx_fsm_resetdone,
1417  rxbyteisaligned_quad_array => mgt_rxbyteisaligned,
1418  rxresetdone_quad_array => mgt_rx_resetdone,
1419  txresetdone_quad_array => mgt_tx_resetdone,
1420  loopback_quad_array => mgt_loopback_in,
1421  rxchariscomma_quad_array => mgt_rxchariscomma,
1422  rxcharisk_quad_array => mgt_rxcharisk,
1423  txcharisk_quad_array => mgt_txcharisk,
1424  txbufstatus_quad_array => mgt_txbufstatus,
1425  rxbyterealign_quad_array => mgt_rxbyterealign,
1426  rxcommadet_quad_array => mgt_rxcommadet,
1427  rxdisperr_quad_array => mgt_rxdisperr(19 downto 0), --what about the other bits?
1428  rxnotintable_quad_array => mgt_rxnotintable(19 downto 0),
1429  mgt_QPLLREFCLKLOST_OUT => mgt_QPLLREFCLKLOST_OUT,
1430  mgt_QPLLLOCK_OUT => mgt_QPLLLOCK_OUT
1431  );
1432 
1433 
1434 
1435 -----------------------------------------------------------------------------------
1436 --- MGT tx_rx ipbus connections
1437 ------------------------------------------------------------------------------------
1438  MGT_ipb : entity infrastructure_lib.mgt_slaves
1439  generic map (
1440  MGT_QUAD_ENABLE => F_MGT_QUAD_ENABLE(FLAVOUR),
1441  MGT_USE_OTHER_CLK => F_MGT_USE_OTHER_CLK(FLAVOUR),
1442  MGT_TX_POWER => F_MGT_TX_POWER(FLAVOUR),
1443  MGT_RX_POWER => F_MGT_RX_POWER(FLAVOUR)
1444  )
1445  port map (
1446  clk280_rx => mgt_RXUSRCLK_OUT,
1447  clk280_tx => mgt_TXUSRCLK_OUT,
1448  clk280 => clk280,
1449  BCR_in => BCR_i,
1450  clk40 => clk40,
1451  ipb_clk => ipb_clk,
1452  ipb_rst => rst_ipb,
1453  ipb_in => ipbw(N_SLV_EFEX_MGT_TOP),
1454  ipb_out => ipbr(N_SLV_EFEX_MGT_TOP),
1455  --mgt quad
1456  bc_cntr_0 => bc_cntr_0,
1457  bc_cntr_1 => bc_cntr_1,
1458  bc_cntr_2 => bc_cntr_2,
1459  bc_cntr_3 => bc_cntr_3,
1460  bc_mux_cntr_0 => bc_mux_cntr_0,
1461  bc_mux_cntr_1 => bc_mux_cntr_1,
1462  bc_mux_cntr_2 => bc_mux_cntr_2,
1463  bc_mux_cntr_3 => bc_mux_cntr_3,
1464  delay_cntr => delay_num,
1465  mgt_enable => enable_mgt,
1466  phase_mux => phase_mux,
1467  --error_counter => error_counter,
1468  loopback => mgt_loopback_reg,
1469  bc_reg_sel => bc_reg_sel,
1470  mux_sel => mux_sel,
1471  softreset_tx => mgt_SOFT_RESET_TX_IN,
1472  softreset_rx => mgt_SOFT_RESET_RX_IN,
1473  qpll_lock => mgt_QPLLLOCK_OUT,
1474  qpll_refclklost => mgt_QPLLREFCLKLOST_OUT,
1475  rx_resetdone => rx_resetdone,
1476  rx_fsm_resetdone => mgt_rx_fsm_resetdone,
1477  rx_byteisaligned => rxbyteisaligned,
1478  crc_error_chan => crc_error_chan,
1479  tx_resetdone => tx_resetdone,
1480  tx_fsm_resetdone => mgt_tx_fsm_resetdone,
1481  tx_bufstatus => tx_bufstatus,
1482  rx_realign => rx_realign,
1483  kchar_mgt => kchar_mgt,
1484  rxdata_mgt0 => rxdata_mgt0,
1485  ram_data_mgt0 => ram_data_mgt0,
1486  rxdata_mgt1 => rxdata_mgt1,
1487  ram_data_mgt1 => ram_data_mgt1,
1488  rxdata_mgt2 => rxdata_mgt2,
1489  ram_data_mgt2 => ram_data_mgt2,
1490  rxdata_mgt3 => rxdata_mgt3,
1491  ram_data_mgt3 => ram_data_mgt3,
1492  rx_disperr => rx_disperr, --(63 downto 0),
1493  encode_error => encode_error, --(63 downto 0)
1494 
1495  disperr_error => disperr_error_i,
1496  notable_error => notable_error_i
1497 
1498  );
1499 end generate;
1500 -- ILA_disperr_error : ila_ipbus_fabric_rd_wr
1501 -- port map (
1502 -- clk => clk280,
1503 -- probe0 => disperr_error_i(35 downto 0), --36b
1504 -- probe1 => disperr_error_i(71 downto 36), --36b
1505 -- probe2(0) => L1A_i, -- 1b
1506 -- probe3(0) => '0', -- 1b
1507 -- probe4(0) => '0', -- 1b
1508 -- probe5(7 downto 0) => disperr_error_i(79 downto 72), --36b
1509 -- probe5(35 downto 8) => (others => '0'), --36b
1510 -- probe6 => (others => '0'), --36b
1511 -- probe7(0) => '0', -- 1b
1512 -- probe8(0) => BCR_i, -- 1b
1513 -- probe9(0) => '0' -- 1b
1514 -- );
1515 
1516 
1517 
1518 ------------------------------------------------------------------
1519 --global merge signalsf12abe46c9c5cf1e601e3ae880fbaf4a886a093d
1520  GLOBAL_MERGE : if MERGE_ENABLED and (FLAVOUR = 1 or FLAVOUR = 2) generate
1521 
1522  TOB_BCN_sync <= TOB_BCN_sync_eg_i when FLAVOUR = 1 else TOB_BCN_sync_tau_i;
1523  sorted_Start_sel <= sorted_eg_Start when FLAVOUR = 1 else sorted_tau_Start;
1524  sorted_TOB_sel <= sorted_eg_TOB when FLAVOUR = 1 else sorted_tau_TOB;
1525  sorted_Valid_sel <= sorted_eg_Valid when FLAVOUR = 1 else sorted_tau_Valid;
1526 
1527  proc_clk_280 : process (clk280)
1528  begin
1529  if rising_edge (clk280) then
1530  data_merge_BCN_A_i <= data_from_fpga_A(32); -- pipeline 1 tick
1531  data_merge_BCN_B_i <= data_from_fpga_B(32); -- pipeline 1 tick
1532  data_merge_BCN_C_i <= data_from_fpga_C(32); -- pipeline 1 tick
1533  data_merge_i(0) <= sorted_TOB_sel;
1534  data_merge_i(1) <= data_from_fpga_A(31 downto 0);
1535  data_merge_i(2) <= data_from_fpga_B(31 downto 0);
1536  data_merge_i(3) <= data_from_fpga_C(31 downto 0);
1537  TOB_BCN_sync_i <= TOB_BCN_sync;
1538  sorted_Start_sel_i <= sorted_Start_sel;
1539  sorted_TOB_BCN_i <= sorted_TOB_BCN;
1540 
1541  data_merge_BCN_A_ii <= data_merge_BCN_A_i; -- pipeline 1 tick
1542  data_merge_BCN_B_ii <= data_merge_BCN_B_i; -- pipeline 1 tick
1543  data_merge_BCN_C_ii <= data_merge_BCN_C_i; -- pipeline 1 tick
1544  data_merge_ii <= data_merge_i;
1545  TOB_BCN_sync_ii <= TOB_BCN_sync_i;
1546  sorted_Start_sel_ii <= sorted_Start_sel_i;
1547  sorted_TOB_BCN_ii <= sorted_TOB_BCN_i;
1548 
1549  end if;
1550  end process;
1551 
1552 
1553  Merging_Module : entity algolib.IPBusTopMergingModule -- merging module of TOBs
1554  port map (
1555  CLK => clk280,
1556 
1557  IN_Data => data_merge_ii,
1558  IN_BCN_sync(0) => data_merge_BCN_A_ii,
1559  IN_BCN_sync(1) => data_merge_BCN_B_ii,
1560  IN_BCN_sync(2) => data_merge_BCN_C_ii,
1561  IN_BCN_sync(3) => TOB_BCN_sync_ii,
1562  IN_Sync => sorted_Start_sel_ii,
1563  IN_local_BCN => sorted_TOB_BCN_ii,
1564 
1565  OUT_merged_BCN => merged_TOB_BCN_i,
1566 
1567  --IPBus connection
1568  ipb_clk => ipb_clk,
1569  ipb_rst => rst_ipb,
1570  ipb_in => ipbw(N_SLV_EFEX_MERGING),
1571  ipb_out => ipbr(N_SLV_EFEX_MERGING),
1572  OUT_Sync => sorted_merged_Start,
1573  OUT_Valid => sorted_merged_Valid,
1574  OUT_TOB => sorted_merged_TOB
1575  );
1576 
1577  --------------------------------------------------------------------------------------
1578  ---- tob data phase adjusting with tx clock
1579  ----------------------------------------------------------------------------------------
1580  tx_phase_adjust : entity infrastructure_lib.efex_topo_tx --top_tx_alignment
1581  generic map (NCOUNTERS => 12)
1582  port map(
1583  clk280 => clk280,
1584  reset => control_reg(5),
1585  --tx_clk => mgt_sel_tx_clk,
1586  rst => reset,
1587  bcn => merged_TOB_BCN_i(3 downto 0), -- bcn from the merging block
1588  sorted_sync => sorted_merged_Start,
1589  sorted_synch_int => sorted_synch_int,
1590  tob_data => sorted_merged_TOB,
1591  sorted_valid => sorted_merged_Valid,
1592  tx_datai_0 => txdatai_0,
1593  tx_datai_1 => txdatai_1,
1594  tx_datai_2 => txdatai_2,
1595  tx_datai_3 => txdatai_3,
1596  tx_datai_4 => txdatai_4,
1597  tx_datai_5 => txdatai_5,
1598  tx_datai_6 => txdatai_6,
1599  tx_datai_7 => txdatai_7,
1600  tx_datai_8 => txdatai_8,
1601  tx_datai_9 => txdatai_9,
1602  tx_datai_10 => txdatai_10,
1603  tx_datai_11 => txdatai_11
1604  );
1605 
1606  -- ILA_latency_rxusrclk : ila_ipbus_fabric_rd_wr
1607  -- port map (
1608  -- clk => mgt_RXUSRCLK_OUT(18) ,
1609  -- probe0(31 downto 0) => sorted_merged_TOB(31 downto 0), --36b
1610  -- probe0(35 downto 32) => (others => '0'), --36b
1611  -- probe1(33 downto 0) => txdatai_0, --36b
1612  -- probe1(34) => '0', --36b
1613  -- probe1(35) => latency_check_out, --36b
1614  -- probe2(0) => L1A_i, -- 1b
1615  -- probe3(0) => sorted_merged_Valid, -- 1b
1616  -- probe4(0) => latency_check_in, -- 1b
1617  -- probe5(31 downto 0) => data_merge_ii(0) , --36b input of merging local
1618  -- probe5(35 downto 32) => "0000", --36b
1619  -- probe6(31 downto 0) => rxdata_quad_array(4).gt2_rxdata_out, --36b
1620  -- probe6(35 downto 32) => "0000", --36b
1621  -- probe7(0) => sorted_merged_Start, -- 1b
1622  -- probe8(0) => BCR_i, -- 1b
1623  -- probe9(0) => mgt_commadet_int(18) -- 1b
1624  -- );
1625 
1626 -- ILA_latency_280clk : ila_ipbus_fabric_rd_wr
1627 -- port map (
1628 -- clk => clk280,
1629 -- probe0(31 downto 0) => data_merge_ii(0) , --36b input of merging local
1630 -- probe0(35 downto 32) => (others => '0'), --36b
1631 -- probe1(31 downto 0) => data_merge_ii(1) , --36b input of merging U1 or U2 input
1632 -- probe1(32) => sorted_Start_sel_ii, --36b input of merging
1633 -- probe1(35 downto 33) => (others => '0'), --36b
1634 -- probe2(0) => L1A_i, -- 1b
1635 -- probe3(0) => sorted_merged_Valid, -- 1b output of merging
1636 -- probe4(0) => sorted_eg_Start, -- 1b output of sorting
1637 -- probe5(31 downto 0) => sorted_eg_TOB, --36b output of sorting
1638 -- probe5(35 downto 32) => "0000", --36b
1639 -- probe6(31 downto 0) => sorted_merged_TOB(31 downto 0), --36b output of merging
1640 -- probe6(35 downto 32) => (others => '0'), --36b
1641 -- probe7(0) => sorted_merged_Start, -- 1b output of merging
1642 -- probe8(0) => BCR_i, -- 1b
1643 -- probe9(0) => mgt_commadet_int(18) -- 1b output of sorting
1644 -- );
1645 
1646 ila_clk_proc : process (clk280)
1647  begin
1648  if clk280'event AND clk280 = '1' then
1649  latency_check_in <= '1' when (rxdata_quad_array(4).gt2_rxdata_out(19 downto 0) = X"55400") else '0';
1650  latency_check_out <= '1' when (txdatai_0(11 downto 0) = X"062") else '0';
1651  end if;
1652  end process;
1653 
1654  IO_DELAY_A1 : io_delay
1655  port map
1656  (
1657  data_in_from_pins_p => data_from_fpga_A_p(15 downto 0),
1658  data_in_from_pins_n => data_from_fpga_A_n(15 downto 0),
1659  data_in_to_device => data_from_fpga_A(15 downto 0),
1660 
1661  delay_clk => clk280,
1662  in_delay_reset => tob_delay_reg(24),
1663  in_delay_data_ce => (others => '0'),
1664  in_delay_data_inc => (others => '0'),
1665  in_delay_tap_in => tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&
1666  tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&
1667  tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&
1668  tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0),
1669  in_delay_tap_out(4 downto 0) => tob_delay_status(4 downto 0),
1670  in_delay_tap_out(79 downto 5) => dummy1,
1671  delay_locked => tob_delay_status(24),
1672  ref_clock => clk200_iodelay,
1673  clk_in => clk280,
1674  io_reset => tob_delay_reg(28)
1675  );
1676  IO_DELAY_A2 : io_delay
1677  port map
1678  (
1679  data_in_from_pins_p => data_from_fpga_A_p(31 downto 16),
1680  data_in_from_pins_n => data_from_fpga_A_n(31 downto 16),
1681  data_in_to_device => data_from_fpga_A(31 downto 16),
1682 
1683  delay_clk => clk280,
1684  in_delay_reset => tob_delay_reg(24),
1685  in_delay_data_ce => (others => '0'),
1686  in_delay_data_inc => (others => '0'),
1687  in_delay_tap_in => tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&
1688  tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&
1689  tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&
1690  tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0)&tob_delay_reg(4 downto 0),
1691  in_delay_tap_out => open,
1692 
1693  delay_locked => tob_delay_status(25),
1694  ref_clock => clk200_iodelay,
1695  clk_in => clk280,
1696  io_reset => tob_delay_reg(28)
1697  );
1698 
1699 -----B
1700  IO_DELAY_B1 : io_delay
1701  port map
1702  (
1703  data_in_from_pins_p => data_from_fpga_B_p(15 downto 0),
1704  data_in_from_pins_n => data_from_fpga_B_n(15 downto 0),
1705  data_in_to_device => data_from_fpga_B(15 downto 0),
1706 
1707  delay_clk => clk280,
1708  in_delay_reset => tob_delay_reg(24),
1709  in_delay_data_ce => (others => '0'),
1710  in_delay_data_inc => (others => '0'),
1711  in_delay_tap_in => tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&
1712  tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&
1713  tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&
1714  tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8),
1715  in_delay_tap_out(4 downto 0) => tob_delay_status(12 downto 8),
1716  in_delay_tap_out(79 downto 5) => dummy2,
1717  delay_locked => tob_delay_status(26),
1718  ref_clock => clk200_iodelay,
1719  clk_in => clk280,
1720  io_reset => tob_delay_reg(28)
1721  );
1722  IO_DELAY_B2 : io_delay
1723  port map
1724  (
1725  data_in_from_pins_p => data_from_fpga_B_p(31 downto 16),
1726  data_in_from_pins_n => data_from_fpga_B_n(31 downto 16),
1727  data_in_to_device => data_from_fpga_B(31 downto 16),
1728 
1729  delay_clk => clk280,
1730  in_delay_reset => tob_delay_reg(24),
1731  in_delay_data_ce => (others => '0'),
1732  in_delay_data_inc => (others => '0'),
1733  in_delay_tap_in => tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&
1734  tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&
1735  tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&
1736  tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8)&tob_delay_reg(12 downto 8),
1737  in_delay_tap_out => open,
1738 
1739  delay_locked => tob_delay_status(27),
1740  ref_clock => clk200_iodelay,
1741  clk_in => clk280,
1742  io_reset => tob_delay_reg(28)
1743  );
1744 
1745 -----C
1746  IO_DELAY_C1 : io_delay
1747  port map
1748  (
1749  data_in_from_pins_p => data_from_fpga_C_p(15 downto 0),
1750  data_in_from_pins_n => data_from_fpga_C_n(15 downto 0),
1751  data_in_to_device => data_from_fpga_C(15 downto 0),
1752 
1753  delay_clk => clk280,
1754  in_delay_reset => tob_delay_reg(24),
1755  in_delay_data_ce => (others => '0'),
1756  in_delay_data_inc => (others => '0'),
1757  in_delay_tap_in => tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&
1758  tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&
1759  tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&
1760  tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16),
1761  in_delay_tap_out(4 downto 0) => tob_delay_status(20 downto 16),
1762  in_delay_tap_out(79 downto 5) => dummy3,
1763 
1764  delay_locked => tob_delay_status(28),
1765  ref_clock => clk200_iodelay,
1766  clk_in => clk280,
1767  io_reset => tob_delay_reg(28)
1768  );
1769 
1770  IO_DELAY_C2 : io_delay
1771  port map
1772  (
1773  data_in_from_pins_p => data_from_fpga_C_p(31 downto 16),
1774  data_in_from_pins_n => data_from_fpga_C_n(31 downto 16),
1775  data_in_to_device => data_from_fpga_C(31 downto 16),
1776 
1777  delay_clk => clk280,
1778  in_delay_reset => tob_delay_reg(24),
1779  in_delay_data_ce => (others => '0'),
1780  in_delay_data_inc => (others => '0'),
1781  in_delay_tap_in => tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&
1782  tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&
1783  tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&
1784  tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16)&tob_delay_reg(20 downto 16),
1785  in_delay_tap_out => open,
1786 
1787  delay_locked => tob_delay_status(29),
1788  ref_clock => clk200_iodelay,
1789  clk_in => clk280,
1790  io_reset => tob_delay_reg(28)
1791  );
1792 
1793  IO_DELAY_BC_A : io_delay2
1794  port map
1795  (
1796  data_in_from_pins_p(0) => data_from_fpga_A_p(32),
1797  data_in_from_pins_n(0) => data_from_fpga_A_n(32),
1798  data_in_to_device(0) => data_from_fpga_A(32),
1799 
1800  delay_clk => clk280,
1801  in_delay_reset => tob_bc_reg(24),
1802  in_delay_data_ce => (others => '0'),
1803  in_delay_data_inc => (others => '0'),
1804  in_delay_tap_in => tob_bc_reg(4 downto 0),
1805  in_delay_tap_out => tob_bc_status(4 downto 0),
1806  delay_locked => tob_bc_status(24),
1807  ref_clock => clk200_iodelay,
1808  clk_in => clk280,
1809  io_reset => tob_delay_reg(28)
1810  );
1811 
1812  IO_DELAY_BC_B : io_delay2
1813  port map
1814  (
1815  data_in_from_pins_p(0) => data_from_fpga_B_p(32),
1816  data_in_from_pins_n(0) => data_from_fpga_B_n(32),
1817  data_in_to_device(0) => data_from_fpga_B(32),
1818 
1819  delay_clk => clk280,
1820  in_delay_reset => tob_bc_reg(25),
1821  in_delay_data_ce => (others => '0'),
1822  in_delay_data_inc => (others => '0'),
1823  in_delay_tap_in => tob_bc_reg(12 downto 8),
1824  in_delay_tap_out => tob_bc_status(12 downto 8),
1825  delay_locked => tob_bc_status(25),
1826  ref_clock => clk200_iodelay,
1827  clk_in => clk280,
1828  io_reset => tob_delay_reg(28)
1829  );
1830 
1831  IO_DELAY_BC_C : io_delay2
1832  port map
1833  (
1834  data_in_from_pins_p(0) => data_from_fpga_C_p(32),
1835  data_in_from_pins_n(0) => data_from_fpga_C_n(32),
1836  data_in_to_device(0) => data_from_fpga_C(32),
1837 
1838  delay_clk => clk280,
1839  in_delay_reset => tob_bc_reg(26),
1840  in_delay_data_ce => (others => '0'),
1841  in_delay_data_inc => (others => '0'),
1842  in_delay_tap_in => tob_bc_reg(20 downto 16),
1843  in_delay_tap_out => tob_bc_status(20 downto 16),
1844  delay_locked => tob_bc_status(26),
1845  ref_clock => clk200_iodelay,
1846  clk_in => clk280,
1847  io_reset => tob_delay_reg(28)
1848  );
1849  else generate
1850  ipbr(N_SLV_EFEX_MERGING) <= IPB_RBUS_NULL;
1851 
1852  end generate GLOBAL_MERGE;
1853 ------------------------------------------------------------------------
1854 
1855 -- resetbc_cntr <= mgt_SOFT_RESET_RX_IN(0) or mgt_SOFT_RESET_RX_IN(0);
1856 
1857 -- ILA_bcn_l1A_id : ila_ipbus_fabric_rd_wr
1858 -- port map (
1859 -- clk => clk40,
1860 -- probe0 => (others => '0'), --36b
1861 -- probe1 => (others => '0'), --36b
1862 -- probe2(0) => L1A_i, -- 1b
1863 -- probe3 => (others => '0'), -- 1b
1864 -- probe4 => (others => '0'), -- 1b
1865 -- probe5 => (others => '0'), --36b
1866 -- probe6(11 downto 0) => bcn_cntr, --36b
1867 -- probe6(31 downto 12) => (others => '0'), --36b
1868 -- probe7(0) => BCR_i, -- 1b
1869 -- probe8 => (others => '0'), -- 1b
1870 -- probe9(0) => ECR_i -- 1b
1871 -- );
1872 
1873 
1874 -- scope : ila_0
1875 -- port map (
1876 -- clk => clk280,
1877 -- probe0(31 downto 0) => TOPO_TOB_out,
1878 -- probe0(63 downto 32) => RAW_Data_out,
1879 -- probe0(64) => RAW_Data_out_char,
1880 -- probe0(65) => TOPO_TOB_out_char
1881 -- );
1882 
1883 
1884 -- scope : ila_0
1885 -- port map (
1886 -- clk => clk280,
1887 -- probe0(31 downto 0) => txdatai_0(31 downto 0),
1888 -- probe0(63 downto 32) => T_TOB_32b_in_i,
1889 -- probe0(64) => txdatai_0(32),
1890 -- probe0(65) => T_TOB_sync_in_i,
1891 -- probe0 (66) => T_TOB_wr_in_i,
1892 -- probe0 (70 downto 67) => sorted_TOB_BCN_i(3 downto 0),
1893 -- probe0(71) => sorted_synch_int
1894 
1895 -- );
1896 
1897 
1898 
1899 --your_instance_name : ila_inputRam
1900 --PORT MAP (
1901 --clk => clk40,
1902 -- probe0(6 downto 0) => ila_bcn(6 downto 0),
1903 -- probe0(18 downto 7) => bcn_cntr_i,
1904 -- probe0(19) => bcr_i
1905 -- );
1906 
1907 end Behavioral;
AlgoDataTypes
External data-types and functions.
Definition: AlgoDataTypes.vhd:15
AlgoDataTypes.AlgoTriggerObjects
array(natural range <> ) of AlgoTriggerObject AlgoTriggerObjects
Algorithm OUTPUT port.
Definition: AlgoDataTypes.vhd:122
AlgoDataTypes.AlgoTriggerObject
std_logic_vector( OUT_TOB_WIDTH- 1 downto 0) AlgoTriggerObject
Algorithm Trigger Object TOB.
Definition: AlgoDataTypes.vhd:120
AlgoDataTypes.AlgoXOutput
( OUTPUT_TOBS- 1 downto 0) AlgoXTriggerObject AlgoXOutput
Algorithm XOUTPUT port.
Definition: AlgoDataTypes.vhd:128
EfexDataFormats
eFEX data-types and functions
Definition: efex_data_formats.vhd:352
IPBusTopMergingModule
Top of TOB merging module with IPBus interface.
Definition: IPBusTopMergingModule.vhd:25
MGT_4_quad_gen
MGT quad generation.
Definition: MGT_4_quad_gen.vhd:43
Readout_logic_top
Top Level of Readout Logic for process FPGA.
Definition: Readout_logic_top.vhd:112
Readout_logic_top.RAW_data_out
out RAW_data_out STD_LOGIC_VECTOR( 31 downto 0)
calorimeter data 32b out to MGT
Definition: Readout_logic_top.vhd:209
Readout_logic_top.RST
in RST std_logic
Reset from 40MHz MMCM lock signal.
Definition: Readout_logic_top.vhd:120
Readout_logic_top.TOB_TXOUTCLK
in TOB_TXOUTCLK STD_LOGIC
TOB TXOUTCLK to read XTOB/TOB data to MGT for transmission to control FPGA.
Definition: Readout_logic_top.vhd:146
Readout_logic_top.ipb_rst
in ipb_rst std_logic
ipb_rst signal is input from master to slaves
Definition: Readout_logic_top.vhd:124
Readout_logic_top.XTOB_tau_in
in XTOB_tau_in AlgoXOutput
XTOBs tau 64b.
Definition: Readout_logic_top.vhd:157
Readout_logic_top.TOB_ready_in
in TOB_ready_in std_logic
Ready signal from control FPGA to receive TOBs data.
Definition: Readout_logic_top.vhd:189
Readout_logic_top.BCR_in
in BCR_in STD_LOGIC
BCR signal input.
Definition: Readout_logic_top.vhd:177
Readout_logic_top.XTOB_tau_Valid_flg_in
in XTOB_tau_Valid_flg_in STD_LOGIC_VECTOR( 7 downto 0)
8b XTOB tau has valid d
Definition: Readout_logic_top.vhd:159
Readout_logic_top.mgt_enable_in
in mgt_enable_in STD_LOGIC_VECTOR( 48 downto 0)
Definition: Readout_logic_top.vhd:202
Readout_logic_top.busy_tob
out busy_tob std_logic
tob data busy out
Definition: Readout_logic_top.vhd:195
Readout_logic_top.XTOB_eg_Valid_flg_in
in XTOB_eg_Valid_flg_in STD_LOGIC_VECTOR( 7 downto 0)
8b XTOB e/g has valid d
Definition: Readout_logic_top.vhd:153
Readout_logic_top.IPb_out
out IPb_out ipb_rbus
IPb_out signal going from slaves to master.
Definition: Readout_logic_top.vhd:130
Readout_logic_top.XTOB_tau_sync_in
in XTOB_tau_sync_in STD_LOGIC
XTOB tau sync sig.
Definition: Readout_logic_top.vhd:161
Readout_logic_top.TTC_L1A_ID_EXT_in
in TTC_L1A_ID_EXT_in STD_LOGIC_VECTOR( 7 downto 0)
Extended L1A ID provided by TTC - ECRID.
Definition: Readout_logic_top.vhd:183
Readout_logic_top.TOB_out
out TOB_out STD_LOGIC_VECTOR( 31 downto 0)
32b sorted XTOB/TOB out to MGT
Definition: Readout_logic_top.vhd:199
Readout_logic_top.clk_load_in
in clk_load_in STD_LOGIC
40Mhz input signal at 20% duty cycle
Definition: Readout_logic_top.vhd:132
Readout_logic_top.T_TOB_32b_in
in T_TOB_32b_in STD_LOGIC_VECTOR( 31 downto 0)
Sorted TOB data readout 32b * 7 in series, only 6 is used - F1 reads e/g TOBs and F2 reads tau TOBs.
Definition: Readout_logic_top.vhd:165
Readout_logic_top.TTC_parity_in
in TTC_parity_in STD_LOGIC
Odd parity over ECR ID and L1A ID provided by TTC.
Definition: Readout_logic_top.vhd:187
Readout_logic_top.T_TOB_sync_in
in T_TOB_sync_in STD_LOGIC
sorted TOB start signal
Definition: Readout_logic_top.vhd:167
Readout_logic_top.L1A_in
in L1A_in STD_LOGIC
L1A signal input.
Definition: Readout_logic_top.vhd:173
Readout_logic_top.OUT_TOB_BCN
in OUT_TOB_BCN std_logic_vector( 6 downto 0)
sorted TOB BC_ID with delay through ALGO/sorting block
Definition: Readout_logic_top.vhd:171
Readout_logic_top.shelf_number
in shelf_number STD_LOGIC_VECTOR( 3 downto 0)
shelf number input
Definition: Readout_logic_top.vhd:142
Readout_logic_top.local_BCN_out
out local_BCN_out STD_LOGIC_VECTOR( 11 downto 0)
Local BCN generated in Process FPGA.
Definition: Readout_logic_top.vhd:181
Readout_logic_top.IPb_in
in IPb_in ipb_wbus
IPb_in signal going from master to slaves.
Definition: Readout_logic_top.vhd:128
Readout_logic_top.efex_slot_num
in efex_slot_num STD_LOGIC_VECTOR( 3 downto 0)
eFEX slot number input
Definition: Readout_logic_top.vhd:144
Readout_logic_top.ipb_clk
in ipb_clk std_logic
ipb_clk signal is input from master to slaves
Definition: Readout_logic_top.vhd:126
Readout_logic_top.XTOB_eg_in
in XTOB_eg_in AlgoXOutput
XTOBs e/g 64b * 8.
Definition: Readout_logic_top.vhd:151
Readout_logic_top.TTC_L1A_ID_in
in TTC_L1A_ID_in STD_LOGIC_VECTOR( 23 downto 0)
L1A ID provided by TTC.
Definition: Readout_logic_top.vhd:185
Readout_logic_top.clk_200M_in
in clk_200M_in STD_LOGIC
200Mhz input signal
Definition: Readout_logic_top.vhd:136
Readout_logic_top.OUT_XTOB_BCN
in OUT_XTOB_BCN std_logic_vector( 6 downto 0)
XTOB BC_ID with delay through ALGO/sorting block.
Definition: Readout_logic_top.vhd:163
Readout_logic_top.FPGA_NUMBER
FPGA_NUMBER integer := 1
Integer used to distinguish different FPGAs having a slightly different firmware.
Definition: Readout_logic_top.vhd:117
Readout_logic_top.TTC_read_all_in
in TTC_read_all_in STD_LOGIC
Privilege Read signal input (previledge read)
Definition: Readout_logic_top.vhd:179
Readout_logic_top.busy_raw
out busy_raw std_logic
raw data busy out
Definition: Readout_logic_top.vhd:193
Readout_logic_top.ECR_in
in ECR_in STD_LOGIC
ECR signal input.
Definition: Readout_logic_top.vhd:175
Readout_logic_top.RAW_ready_in
in RAW_ready_in std_logic
Ready signal from control FPGA to receive RAW calorimeter data.
Definition: Readout_logic_top.vhd:191
Readout_logic_top.clk_40M_in
in clk_40M_in STD_LOGIC
40Mhz input signal
Definition: Readout_logic_top.vhd:140
Readout_logic_top.RAW_TXOUTCLK
in RAW_TXOUTCLK STD_LOGIC
Calorimeter TXOUTCLK to read Calorimeter data to MGT for transmission to control FPGA.
Definition: Readout_logic_top.vhd:148
Readout_logic_top.hw_addr
in hw_addr STD_LOGIC_VECTOR( 1 downto 0)
FPGA Hardware Address.
Definition: Readout_logic_top.vhd:122
Readout_logic_top.TOB_out_is_char
out TOB_out_is_char STD_LOGIC
32b data out to MGT is CHAR
Definition: Readout_logic_top.vhd:197
Readout_logic_top.T_TOB_valid_in
in T_TOB_valid_in STD_LOGIC
sorted TOB valid signal
Definition: Readout_logic_top.vhd:169
Readout_logic_top.RAW_data_in
in RAW_data_in RAW_data_227_type
calorimeter data array 49 x 224b input frames
Definition: Readout_logic_top.vhd:204
Readout_logic_top.RAW_out_is_char
out RAW_out_is_char STD_LOGIC
calorimeter data 32b out to MGT is CHAR
Definition: Readout_logic_top.vhd:206
Readout_logic_top.XTOB_eg_sync_in
in XTOB_eg_sync_in STD_LOGIC
XTOB e/g sync sig.
Definition: Readout_logic_top.vhd:155
Readout_logic_top.clk_280M_in
in clk_280M_in STD_LOGIC
280Mhz input signal
Definition: Readout_logic_top.vhd:138
Readout_logic_top.clk_40M_rdout
in clk_40M_rdout STD_LOGIC
40Mhz input signal used only for RAW data readout
Definition: Readout_logic_top.vhd:134
TOB_rdout_ip_pkg
Definition: TOB_rdout_ip_pkg.vhd:34
clk_resources
Clock generating module.
Definition: clk_resources.vhd:25
clk_resources.TTC_clk_p
in TTC_clk_p std_logic
TTC clock input 40MHz.
Definition: clk_resources.vhd:32
clk_resources.rst_ipb
out rst_ipb std_logic
Reset output synchronised to ipbus clock.
Definition: clk_resources.vhd:52
clk_resources.clk280
out clk280 std_logic
280MHz clock output
Definition: clk_resources.vhd:44
clk_resources.reset
in reset std_logic
Reset output generated from TTC clock MMCM.
Definition: clk_resources.vhd:50
clk_resources.reset_clk125
in reset_clk125 std_logic
External reset signal for 125 MHz clock domain from Control FPGA.
Definition: clk_resources.vhd:36
clk_resources.ipb_clk
out ipb_clk std_logic
31.25MHz clock output used for ipbus communication and accessing registers
Definition: clk_resources.vhd:60
clk_resources.load
out load std_logic
40MHz clock output with 12% duty cycle used in ALGO Block
Definition: clk_resources.vhd:54
clk_resources.clk40_rdout
out clk40_rdout std_logic
40MHz clock output dedicated to Readout Logic
Definition: clk_resources.vhd:38
clk_resources.TTC_clk_n
in TTC_clk_n std_logic
TTC clock input 40MHz.
Definition: clk_resources.vhd:34
clk_resources.gt_clk_p
in gt_clk_p std_logic
Crystal clock input 125MHz.
Definition: clk_resources.vhd:28
clk_resources.mac_clk
out mac_clk std_logic
125MHz clock output for ipbus communication between FPGAs
Definition: clk_resources.vhd:56
clk_resources.onehz
out onehz std_logic
One Hz clock output.
Definition: clk_resources.vhd:48
clk_resources.locked_40m
out locked_40m std_logic
40MHz clock Locked output
Definition: clk_resources.vhd:58
clk_resources.clk200
out clk200 std_logic
200MHz clock output (TTC)
Definition: clk_resources.vhd:40
clk_resources.clk200_iodelay
out clk200_iodelay std_logic
Pure 200MHz clock output.
Definition: clk_resources.vhd:63
clk_resources.rst_macclk
out rst_macclk std_logic
Reset output synchronised to mac clock.
Definition: clk_resources.vhd:46
clk_resources.clk40
out clk40 std_logic
40MHz clock output
Definition: clk_resources.vhd:42
clk_resources.gt_clk_n
in gt_clk_n std_logic
Crystal clock input 125MHz.
Definition: clk_resources.vhd:30
common_id_registers
FPGA Common ID Module.
Definition: common_id_registers.vhd:49
common_id_registers.fw_version
in fw_version std_logic_vector( 31 downto 0)
Version of the repository (format: MMmmcccc in hex)
Definition: common_id_registers.vhd:66
common_id_registers.xml_Gitsha
in xml_Gitsha std_logic_vector( 31 downto 0)
Short 7-digit git SHA of the XMLs.
Definition: common_id_registers.vhd:64
common_id_registers.ipb_rst
in ipb_rst std_logic
ipbus reset
Definition: common_id_registers.vhd:54
common_id_registers.fw_Gitsha
in fw_Gitsha std_logic_vector( 31 downto 0)
Short 7-digit git SHA of the repository.
Definition: common_id_registers.vhd:68
common_id_registers.Module_ID
in Module_ID std_logic_vector( 31 downto 0)
module id of the eFEX
Definition: common_id_registers.vhd:60
common_id_registers.build_date
in build_date std_logic_vector( 31 downto 0)
Date format DDMMYYYY in decimal.
Definition: common_id_registers.vhd:70
common_id_registers.build_time
in build_time std_logic_vector( 31 downto 0)
Time format 00HHMMSS in decimal.
Definition: common_id_registers.vhd:74
common_id_registers.ipb_clk
in ipb_clk std_logic
ipbus clk of 31.25MHz
Definition: common_id_registers.vhd:52
common_id_registers.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to m.
Definition: common_id_registers.vhd:58
common_id_registers.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: common_id_registers.vhd:56
common_id_registers.xml_version
in xml_version std_logic_vector( 31 downto 0)
Version of the XMLs.
Definition: common_id_registers.vhd:62
data_path_block
Data path block.
Definition: data_path_block.vhd:45
data_path_block.ttc_clk
in ttc_clk std_logic
40 MHz clk
Definition: data_path_block.vhd:61
data_path_block.OUT_sorted_eg_TOB
out OUT_sorted_eg_TOB AlgoTriggerObject
Sorted eg TOB 32bit.
Definition: data_path_block.vhd:112
data_path_block.RAW_data
out RAW_data RAW_data_227_type
RAW data to Readout.
Definition: data_path_block.vhd:91
data_path_block.reset
in reset std_logic
syncronous reset used in data_alignment
Definition: data_path_block.vhd:60
data_path_block.ipb_rst
in ipb_rst std_logic
ipbus reset
Definition: data_path_block.vhd:65
data_path_block.OUT_TOB_BCN
out OUT_TOB_BCN std_logic_vector( 11 downto 0)
BCN @280 MHZ referring to 7 TOBS in the BC.
Definition: data_path_block.vhd:120
data_path_block.OUT_eg_Valid
out OUT_eg_Valid std_logic_vector( OUTPUT_TOBS- 1 downto 0)
Valid signal for eg XTOBS @200MHz.
Definition: data_path_block.vhd:95
data_path_block.rx_clk280
in rx_clk280 std_logic_vector( n_channels- 1 downto 0)
MGT clocks.
Definition: data_path_block.vhd:58
data_path_block.OUT_sorted_eg_Valid
out OUT_sorted_eg_Valid std_logic
Sorted TOB valid @280.
Definition: data_path_block.vhd:114
data_path_block.OUT_sorted_tau_Valid
out OUT_sorted_tau_Valid std_logic
Sorted TOB valid @280.
Definition: data_path_block.vhd:119
data_path_block.BC_Reg_sel
in BC_Reg_sel std_logic_vector( 255 downto 0)
16-b BC MUX select for 16 Quads
Definition: data_path_block.vhd:75
data_path_block.OUT_XTOB_BCN
out OUT_XTOB_BCN std_logic_vector( 11 downto 0)
XTOB BCN @200 MHZ referring to 5 TOBS in the BC.
Definition: data_path_block.vhd:109
data_path_block.OUT_sorted_tau_Sync
out OUT_sorted_tau_Sync std_logic
Sorted TOB synch @280 marking first TOB of 7.
Definition: data_path_block.vhd:118
data_path_block.OUT_sorted_tau_TOB
out OUT_sorted_tau_TOB AlgoTriggerObject
Sorted eg TOB 32bit.
Definition: data_path_block.vhd:117
data_path_block.ipb_in_algo
in ipb_in_algo ipb_wbus
ipbus connection for algorithm
Definition: data_path_block.vhd:66
data_path_block.ipb_out_algo
out ipb_out_algo ipb_rbus
ipbus connection for algorithm
Definition: data_path_block.vhd:67
data_path_block.OUT_tau_XTOB
out OUT_tau_XTOB AlgoXOutput
tau XTOBS 8 x 64bit @200MHz
Definition: data_path_block.vhd:106
data_path_block.mux_sel
in mux_sel std_logic_vector( 255 downto 0)
16-b 1st stage MUX select for 16 Quads
Definition: data_path_block.vhd:76
data_path_block.OUT_eg_XTOB
out OUT_eg_XTOB AlgoXOutput
eg XTOBS 8 x 64bit @200MHz
Definition: data_path_block.vhd:99
data_path_block.OUT_eg_Sync
out OUT_eg_Sync std_logic
Sync signal for XTOBS @200MHz marking the first XTOB of 5.
Definition: data_path_block.vhd:97
data_path_block.ipb_in_sorting
in ipb_in_sorting ipb_wbus
ipbus connection for local TOB sorting
Definition: data_path_block.vhd:68
data_path_block.OUT_tau_Valid
out OUT_tau_Valid std_logic_vector( OUTPUT_TOBS- 1 downto 0)
Valid signal for eg XTOBS @200MHz.
Definition: data_path_block.vhd:102
data_path_block.OUT_tau_Sync
out OUT_tau_Sync std_logic
Sync signal for XTOBS @200MHz marking the first XTOB of 5.
Definition: data_path_block.vhd:104
data_path_block.clk280
in clk280 std_logic
Used in the output stage of the algorithm.
Definition: data_path_block.vhd:59
data_path_block.rx_resetdone
in rx_resetdone std_logic_vector( n_channels- 1 downto 0)
reset done from GMTs
Definition: data_path_block.vhd:78
data_path_block.ipb_clk
in ipb_clk std_logic
ipbus clock
Definition: data_path_block.vhd:64
data_path_block.ipb_out_sorting
out ipb_out_sorting ipb_rbus
ipbus connection for local TOB sorting
Definition: data_path_block.vhd:69
data_path_block.OUT_sorted_eg_Sync
out OUT_sorted_eg_Sync std_logic
Sorted TOB synch @280 marking first TOB of 7.
Definition: data_path_block.vhd:113
data_path_block.sel_bcn_or_bc_cnt
in sel_bcn_or_bc_cnt std_logic
selects between real data BC value (1) and BC delay counter (0) to ipbus
Definition: data_path_block.vhd:73
data_path_block.enable_mgt
in enable_mgt std_logic_vector( n_channels- 1 downto 0)
MGT enable.
Definition: data_path_block.vhd:77
data_path_block.pseudo_orbit
out pseudo_orbit std_logic
Pulse generated when 5-bit BCN is 00000.
Definition: data_path_block.vhd:74
data_type_pkg
Definition: data_type_pkg.vhd:34
efex_topo_tx
efex topo protocol
Definition: efex_topo_tx.vhd:21
efex_topo_tx.reset
in reset std_logic
reset
Definition: efex_topo_tx.vhd:28
efex_topo_tx.sorted_valid
in sorted_valid std_logic
Output data valid, high when correspondent output data are valid.
Definition: efex_topo_tx.vhd:40
efex_topo_tx.sorted_sync
in sorted_sync std_logic
Output sync, high on the first clock cycle of the BC.
Definition: efex_topo_tx.vhd:32
efex_topo_tx.tx_datai_0
out tx_datai_0 std_logic_vector( 33 downto 0)
Output data to the mgt that transimits to the L1Topo.
Definition: efex_topo_tx.vhd:42
efex_topo_tx.clk280
in clk280 std_logic
clock 280MHz
Definition: efex_topo_tx.vhd:26
efex_topo_tx.NCOUNTERS
NCOUNTERS integer := 12
number of tx mgts
Definition: efex_topo_tx.vhd:23
efex_topo_tx.bcn
in bcn std_logic_vector( 3 downto 0)
bcn from algo block
Definition: efex_topo_tx.vhd:36
efex_topo_tx.tob_data
in tob_data std_logic_vector( 31 downto 0)
Algorithm external data structure, defined in AlgoDataTypes.vhd.
Definition: efex_topo_tx.vhd:38
efex_topo_tx.sorted_synch_int
out sorted_synch_int std_logic
internally generated out put synch
Definition: efex_topo_tx.vhd:34
efex_topo_tx.rst
in rst std_logic
input reset generated by the not locked 40MHz MMC
Definition: efex_topo_tx.vhd:30
golden
Definition: golden.vhd:5
ipbus_decode_L1CaloEfexProcessor
Definition: ipbus_decode_L1CaloEfexProcessor.vhd:14
lib_registers
Version of the various firmware libraries.
Definition: lib_registers.vhd:15
mgt_slaves
MGT ipbus control.
Definition: mgt_slaves.vhd:34
mgt_slaves.ram_data_mgt0
out ram_data_mgt0 std_logic_vector( 4559 downto 0)
ram data from all channel 0 in the all channels
Definition: mgt_slaves.vhd:133
mgt_slaves.delay_cntr
in delay_cntr std_logic_vector( 319 downto 0)
first stage delay counters
Definition: mgt_slaves.vhd:97
mgt_slaves.kchar_mgt
out kchar_mgt std_logic_vector( 79 downto 0)
kchar_mgt all MGTs
Definition: mgt_slaves.vhd:123
mgt_slaves.rx_fsm_resetdone
in rx_fsm_resetdone std_logic_vector( 79 downto 0)
rx_fsm_resetdone for all MGTs
Definition: mgt_slaves.vhd:105
mgt_slaves.bc_mux_cntr_2
in bc_mux_cntr_2 std_logic_vector( 139 downto 0)
bc_mux_cntr_2 for gt2 of the MGTs
Definition: mgt_slaves.vhd:91
mgt_slaves.clk40
in clk40 std_logic
fabric clock of 40MHz
Definition: mgt_slaves.vhd:53
mgt_slaves.ipb_rst
in ipb_rst std_logic
ipbus reset
Definition: mgt_slaves.vhd:59
mgt_slaves.rxdata_mgt1
in rxdata_mgt1 std_logic_vector( 639 downto 0)
rx data from all gt1 in the all QAUDs
Definition: mgt_slaves.vhd:127
mgt_slaves.BCR_in
in BCR_in std_logic
BCR from TTC information.
Definition: mgt_slaves.vhd:55
mgt_slaves.tx_fsm_resetdone
in tx_fsm_resetdone std_logic_vector( 79 downto 0)
tx_fsm_resetdone for all MGTs
Definition: mgt_slaves.vhd:113
mgt_slaves.qpll_refclklost
in qpll_refclklost std_logic_vector( 19 downto 0)
qpll_refclklost for the quads
Definition: mgt_slaves.vhd:75
mgt_slaves.crc_error_chan
in crc_error_chan std_logic_vector( 79 downto 0)
crc errors for all MGTs
Definition: mgt_slaves.vhd:109
mgt_slaves.rxdata_mgt0
in rxdata_mgt0 std_logic_vector( 639 downto 0)
rx data from all gt0 in the all QAUDs
Definition: mgt_slaves.vhd:125
mgt_slaves.qpll_lock
in qpll_lock std_logic_vector( 19 downto 0)
qpllock for the quads
Definition: mgt_slaves.vhd:73
mgt_slaves.rxdata_mgt3
in rxdata_mgt3 std_logic_vector( 639 downto 0)
rx data from all gt3 in the all QAUDs
Definition: mgt_slaves.vhd:131
mgt_slaves.clk280_rx
in clk280_rx std_logic_vector( 79 downto 0)
rx clock of the all the mgts
Definition: mgt_slaves.vhd:49
mgt_slaves.rx_realign
in rx_realign std_logic_vector( 79 downto 0)
rx_realign for all MGTs
Definition: mgt_slaves.vhd:117
mgt_slaves.bc_cntr_3
in bc_cntr_3 std_logic_vector( 139 downto 0)
bc cntr for all the gt3 of the MGTs
Definition: mgt_slaves.vhd:85
mgt_slaves.softreset_tx
out softreset_tx std_logic_vector( 19 downto 0)
softreset_tx for all the Quads
Definition: mgt_slaves.vhd:67
mgt_slaves.bc_cntr_0
in bc_cntr_0 std_logic_vector( 139 downto 0)
bc cntr for all the gt0 of the MGTs
Definition: mgt_slaves.vhd:79
mgt_slaves.ram_data_mgt2
out ram_data_mgt2 std_logic_vector( 4559 downto 0)
ram data from all channel 2 in the all channels
Definition: mgt_slaves.vhd:137
mgt_slaves.MGT_RX_POWER
MGT_RX_POWER std_logic_vector( 79 downto 0) :=( others => '0')
power down to rx
Definition: mgt_slaves.vhd:44
mgt_slaves.rxdata_mgt2
in rxdata_mgt2 std_logic_vector( 639 downto 0)
rx data from all gt2 in the all QAUDs
Definition: mgt_slaves.vhd:129
mgt_slaves.bc_cntr_1
in bc_cntr_1 std_logic_vector( 139 downto 0)
bc cntr for all the gt1 of the MGTs
Definition: mgt_slaves.vhd:81
mgt_slaves.bc_mux_cntr_1
in bc_mux_cntr_1 std_logic_vector( 139 downto 0)
bc_mux_cntr_1 for gt1 of the MGTs
Definition: mgt_slaves.vhd:89
mgt_slaves.loopback
out loopback std_logic_vector( 59 downto 0)
loopback setting for all the MGTs
Definition: mgt_slaves.vhd:65
mgt_slaves.rx_byteisaligned
in rx_byteisaligned std_logic_vector( 79 downto 0)
rx_byteisaligned for all MGTs
Definition: mgt_slaves.vhd:107
mgt_slaves.rx_resetdone
in rx_resetdone std_logic_vector( 79 downto 0)
rx resetdone for all MGTs
Definition: mgt_slaves.vhd:103
mgt_slaves.bc_cntr_2
in bc_cntr_2 std_logic_vector( 139 downto 0)
bc cntr for all the gt2 of the MGTs
Definition: mgt_slaves.vhd:83
mgt_slaves.disperr_error
out disperr_error std_logic_vector( 79 downto 0)
disperr_error in all the MGTs
Definition: mgt_slaves.vhd:141
mgt_slaves.mgt_enable
out mgt_enable std_logic_vector( 79 downto 0)
mgt enable for the MGTs
Definition: mgt_slaves.vhd:71
mgt_slaves.phase_mux
out phase_mux std_logic_vector( 319 downto 0)
phase_mux
Definition: mgt_slaves.vhd:77
mgt_slaves.tx_resetdone
in tx_resetdone std_logic_vector( 79 downto 0)
tx resetdone for all MGTs
Definition: mgt_slaves.vhd:111
mgt_slaves.tx_bufstatus
in tx_bufstatus std_logic_vector( 159 downto 0)
tx_bufstatus for all MGTs
Definition: mgt_slaves.vhd:115
mgt_slaves.clk280_tx
in clk280_tx std_logic_vector( 79 downto 0)
tx clock of the all the mgts
Definition: mgt_slaves.vhd:47
mgt_slaves.clk280
in clk280 std_logic
fabric clock of clk280MHz
Definition: mgt_slaves.vhd:51
mgt_slaves.MGT_QUAD_ENABLE
MGT_QUAD_ENABLE std_logic_vector( 19 downto 0) := x"00000"
enable the quad in the design
Definition: mgt_slaves.vhd:37
mgt_slaves.ipb_clk
in ipb_clk std_logic
ipbus clock
Definition: mgt_slaves.vhd:57
mgt_slaves.bc_mux_cntr_0
in bc_mux_cntr_0 std_logic_vector( 139 downto 0)
bc_mux_cntr_0 for gt0 of the MGTs
Definition: mgt_slaves.vhd:87
mgt_slaves.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: mgt_slaves.vhd:63
mgt_slaves.mux_sel
out mux_sel std_logic_vector( 319 downto 0)
mux setting for the first stage mux
Definition: mgt_slaves.vhd:101
mgt_slaves.MGT_USE_OTHER_CLK
MGT_USE_OTHER_CLK std_logic_vector( 19 downto 0) := x"00000"
tx or rx clock selection
Definition: mgt_slaves.vhd:39
mgt_slaves.notable_error
out notable_error std_logic_vector( 79 downto 0)
d notable_error in all the MGTs
Definition: mgt_slaves.vhd:145
mgt_slaves.encode_error
in encode_error std_logic_vector( 319 downto 0)
encode_error for all MGTs
Definition: mgt_slaves.vhd:121
mgt_slaves.rx_disperr
in rx_disperr std_logic_vector( 319 downto 0)
rx_disperr for all MGTs
Definition: mgt_slaves.vhd:119
mgt_slaves.bc_mux_cntr_3
in bc_mux_cntr_3 std_logic_vector( 139 downto 0)
bc_mux_cntr_3 for gt3 of the MGTs
Definition: mgt_slaves.vhd:93
mgt_slaves.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: mgt_slaves.vhd:61
mgt_slaves.softreset_rx
out softreset_rx std_logic_vector( 19 downto 0)
softreset_rx for all the Quads
Definition: mgt_slaves.vhd:69
mgt_slaves.MGT_TX_POWER
MGT_TX_POWER std_logic_vector( 79 downto 0) :=( others => '0')
power down to tx
Definition: mgt_slaves.vhd:41
mgt_type
Definition: mgt_type_pkg.vhd:4
self_configure
FPGA Self Reconfigure module.
Definition: self_configure.vhd:19
self_configure.reset
in reset std_logic
Reset input.
Definition: self_configure.vhd:26
self_configure.clk
in clk std_logic
Clock input to ICAP 31.25MHz.
Definition: self_configure.vhd:24
self_configure.indicator
out indicator std_logic
Indicator output signal connected to LED on front panel of eFEX card.
Definition: self_configure.vhd:31
self_configure.WBSTAR
in WBSTAR std_logic_vector( 31 downto 0)
Warm Boot Start Address.
Definition: self_configure.vhd:22
self_configure.trigger
in trigger std_logic
Trigger input to start reconfigureation of the FPGA from the WBSTAR.
Definition: self_configure.vhd:28
slaves
process fpga common slaves
Definition: slave_process_fpga.vhd:22
slaves.tob_delay_reg
out tob_delay_reg std_logic_vector( 31 downto 0)
TOB delay register.
Definition: slave_process_fpga.vhd:42
slaves.ipb_rst
in ipb_rst std_logic
IPBus Reset input.
Definition: slave_process_fpga.vhd:30
slaves.flash_le
out flash_le std_logic
chip select
Definition: slave_process_fpga.vhd:58
slaves.tob_delay_status
in tob_delay_status std_logic_vector( 31 downto 0) :=( others => '0')
TOB delay status register.
Definition: slave_process_fpga.vhd:44
slaves.flash_miso
in flash_miso std_logic
serial input of the spi flash
Definition: slave_process_fpga.vhd:56
slaves.status
in status std_logic_vector( 31 downto 0)
ststus register
Definition: slave_process_fpga.vhd:36
slaves.tob_bc_status
in tob_bc_status std_logic_vector( 31 downto 0) :=( others => '0')
TOB BC delay stataus register.
Definition: slave_process_fpga.vhd:48
slaves.ttc_orbit_length_reg
out ttc_orbit_length_reg std_logic_vector( 31 downto 0)
ttc orbit length
Definition: slave_process_fpga.vhd:54
slaves.ipb_clk
in ipb_clk std_logic
IPBus clock.
Definition: slave_process_fpga.vhd:28
slaves.flash_clko
out flash_clko std_logic
flash clock
Definition: slave_process_fpga.vhd:60
slaves.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: slave_process_fpga.vhd:34
slaves.flash_mosi
out flash_mosi std_logic
serial out of the spi flash
Definition: slave_process_fpga.vhd:62
slaves.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: slave_process_fpga.vhd:32
slaves.tob_bc_reg
out tob_bc_reg std_logic_vector( 31 downto 0)
TOB BC delay register.
Definition: slave_process_fpga.vhd:46
slaves.reconfig_reg
out reconfig_reg std_logic_vector( 31 downto 0)
reconfigure address register
Definition: slave_process_fpga.vhd:50
slaves.TOB_BCN_sych_reg
out TOB_BCN_sych_reg std_logic_vector( 31 downto 0)
TOB_BCN_sych regsiter.
Definition: slave_process_fpga.vhd:40
slaves.bcmuxvalue_sych_reg
out bcmuxvalue_sych_reg std_logic_vector( 31 downto 0)
bc mux value sync
Definition: slave_process_fpga.vhd:52
startup
Startup Block.
Definition: startup.vhd:15
synch_type
Definition: synch_type_pkg.vhd:23
top_efex_processor.Behavioral
Top of the process FPGA.
Definition: top_efex_processor.vhd:202
top_efex_processor.Behavioral.data_to_fpga_Y_n
std_logic_vector( 32 downto 0) data_to_fpga_Y_n
merging data from this fpga to another fpga --
Definition: top_efex_processor.vhd:300
top_efex_processor.Behavioral.data_from_fpga_B_p
std_logic_vector( 32 downto 0) data_from_fpga_B_p
merging data from another fpga
Definition: top_efex_processor.vhd:289
top_efex_processor.Behavioral.ttc_inform_p
std_logic_vector( 3 downto 0) ttc_inform_p
ttc information that has L1A,BCR and ECR
Definition: top_efex_processor.vhd:281
top_efex_processor.Behavioral.busy_tob
std_logic busy_tob
tob data busy out
Definition: top_efex_processor.vhd:302
top_efex_processor.Behavioral.txp_OUT
std_logic_vector( 77 downto 0) txp_OUT
mgts tx side outputs
Definition: top_efex_processor.vhd:296
top_efex_processor.Behavioral.data_from_fpga_B_n
std_logic_vector( 32 downto 0) data_from_fpga_B_n
merging data from another fpga
Definition: top_efex_processor.vhd:290
top_efex_processor.Behavioral.txn_OUT
std_logic_vector( 77 downto 0) txn_OUT
mgts tx side outputs
Definition: top_efex_processor.vhd:295
top_efex_processor.Behavioral.ctrl_TOB_ready_in
std_logic ctrl_TOB_ready_in
Ready signal from control FPGA to receive TOB data.
Definition: top_efex_processor.vhd:285
top_efex_processor.Behavioral.ttc_info
std_logic_vector( 37 downto 0) ttc_info
ttc information ECR ID and L1ID (Phase-I), L0ID (Phase-II)
Definition: top_efex_processor.vhd:283
top_efex_processor.Behavioral.ttc_inform_n
std_logic_vector( 3 downto 0) ttc_inform_n
ttc information that has L1A,BCR and ECR
Definition: top_efex_processor.vhd:282
top_efex_processor.Behavioral.rxn_IN
std_logic_vector( 79 downto 0) rxn_IN
mgt rx side inputs
Definition: top_efex_processor.vhd:279
top_efex_processor.Behavioral.data_from_fpga_A_p
std_logic_vector( 32 downto 0) data_from_fpga_A_p
merging data from another fpga
Definition: top_efex_processor.vhd:287
top_efex_processor.Behavioral.data_from_fpga_A_n
std_logic_vector( 32 downto 0) data_from_fpga_A_n
merging data from another fpga
Definition: top_efex_processor.vhd:288
top_efex_processor.Behavioral.data_to_fpga_Y_p
std_logic_vector( 32 downto 0) data_to_fpga_Y_p
merging data from this fpga to another fpga
Definition: top_efex_processor.vhd:299
top_efex_processor.Behavioral.q_clk_gtrefclk_pad_n_in
std_logic_vector( 19 downto 0) q_clk_gtrefclk_pad_n_in
mgts reference clocks
Definition: top_efex_processor.vhd:277
top_efex_processor.Behavioral.data_from_fpga_C_p
std_logic_vector( 32 downto 0) data_from_fpga_C_p
merging data from another fpga
Definition: top_efex_processor.vhd:291
top_efex_processor.Behavioral.q_clk_gtrefclk_pad_p_in
std_logic_vector( 19 downto 0) q_clk_gtrefclk_pad_p_in
mgts reference clocks
Definition: top_efex_processor.vhd:278
top_efex_processor.Behavioral.busy_raw
std_logic busy_raw
raw data busy out
Definition: top_efex_processor.vhd:301
top_efex_processor.Behavioral.data_from_fpga_C_n
std_logic_vector( 32 downto 0) data_from_fpga_C_n
merging data from another fpga
Definition: top_efex_processor.vhd:292
top_efex_processor.Behavioral.ctrl_RAW_ready_in
std_logic ctrl_RAW_ready_in
Ready signal from control FPGA to receive RAW calorimeter data.
Definition: top_efex_processor.vhd:286
top_efex_processor.Behavioral.data_to_fpga_X_n
std_logic_vector( 32 downto 0) data_to_fpga_X_n
merging data from this fpga to another fpga
Definition: top_efex_processor.vhd:298
top_efex_processor.Behavioral.rxp_IN
std_logic_vector( 79 downto 0) rxp_IN
mgt rx side inputs
Definition: top_efex_processor.vhd:280
top_efex_processor.Behavioral.data_to_fpga_X_p
std_logic_vector( 32 downto 0) data_to_fpga_X_p
merging data from this fpga to another fpga
Definition: top_efex_processor.vhd:297
top_efex_processor.Behavioral.ttc_parity
std_logic ttc_parity
Odd parity over ttc ECRID and L1ID.
Definition: top_efex_processor.vhd:284
top_efex_processor
Top of the process FPGA.
Definition: top_efex_processor.vhd:96
top_efex_processor.INFRASTRUCTURE_LIB_SHA
INFRASTRUCTURE_LIB_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA.
Definition: top_efex_processor.vhd:136
top_efex_processor.reset_clk125
in reset_clk125 std_logic
Reset signal for IPBus clock 125 from Control FPGA.
Definition: top_efex_processor.vhd:185
top_efex_processor.master_tx_pause
in master_tx_pause std_logic
ipbus interconnections signals
Definition: top_efex_processor.vhd:177
top_efex_processor.ALGOLIB_SHA
ALGOLIB_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git sha.
Definition: top_efex_processor.vhd:131
top_efex_processor.IPBUS_LIB_VER
IPBUS_LIB_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of the readout library (format: MMmmpppp in hex)
Definition: top_efex_processor.vhd:148
top_efex_processor.EFEX_POSITION
EFEX_POSITION integer := 0
Possible values: 0 dynamic mapping, 1-3 static mapping.
Definition: top_efex_processor.vhd:167
top_efex_processor.CON_SHA
CON_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA of the tcl file.
Definition: top_efex_processor.vhd:115
top_efex_processor.gt_clk125_n
in gt_clk125_n std_logic
125MHz ipbus clock
Definition: top_efex_processor.vhd:175
top_efex_processor.TOP_VER
TOP_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of the top folder, see TOP_SHA.
Definition: top_efex_processor.vhd:112
top_efex_processor.GLOBAL_SHA
GLOBAL_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA of the repository.
Definition: top_efex_processor.vhd:105
top_efex_processor.TOP_SHA
TOP_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA of the tcl file.
Definition: top_efex_processor.vhd:110
top_efex_processor.GLOBAL_TIME
GLOBAL_TIME std_logic_vector( 31 downto 0) := x"00000000"
Time format 00HHMMSS in decimal.
Definition: top_efex_processor.vhd:103
top_efex_processor.TOB_RDOUT_LIB_VER
TOB_RDOUT_LIB_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of the readout library (format: MMmmpppp in hex)
Definition: top_efex_processor.vhd:143
top_efex_processor.GLOBAL_VER
GLOBAL_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of the repository (format: MMmmpppp in hex)
Definition: top_efex_processor.vhd:107
top_efex_processor.TOB_RDOUT_LIB_SHA
TOB_RDOUT_LIB_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA.
Definition: top_efex_processor.vhd:141
top_efex_processor.GLOBAL_DATE
GLOBAL_DATE std_logic_vector( 31 downto 0) := x"00000000"
Date format DDMMYYYY in decimal.
Definition: top_efex_processor.vhd:101
top_efex_processor.HOG_VER
HOG_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of Hog.
Definition: top_efex_processor.vhd:128
top_efex_processor.ENCODING_MODE
ENCODING_MODE integer := 2
Possible values: -2: Steve's multilinear, -1, Standard multilinear, 0-5 linear encoding shifted by th...
Definition: top_efex_processor.vhd:164
top_efex_processor.HOG_SHA
HOG_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA of the Hog submodule.
Definition: top_efex_processor.vhd:126
top_efex_processor.fpga_geo_addr
in fpga_geo_addr std_logic_vector( 1 downto 0)
geographical address of the fpga
Definition: top_efex_processor.vhd:187
top_efex_processor.gt_clk125_p
in gt_clk125_p std_logic
125MHz ipbus clock
Definition: top_efex_processor.vhd:174
top_efex_processor.INFRASTRUCTURE_LIB_VER
INFRASTRUCTURE_LIB_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of infrastructure library (format: MMmmpppp in hex)
Definition: top_efex_processor.vhd:138
top_efex_processor.XML_VER
XML_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of the XMLs.
Definition: top_efex_processor.vhd:123
top_efex_processor.ALGOLIB_VER
ALGOLIB_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of algolib library (format: MMmmpppp in hex)
Definition: top_efex_processor.vhd:133
top_efex_processor.master_tx_data
out master_tx_data std_logic_vector( 9 downto 0)
ipbus interconnections signals
Definition: top_efex_processor.vhd:178
top_efex_processor.master_rx_data
in master_rx_data std_logic_vector( 9 downto 0)
ipbus interconnections signals
Definition: top_efex_processor.vhd:176
top_efex_processor.FLAVOUR
FLAVOUR integer := 0
Integer used to distinguish different FPGAs having a slightly different firmware.
Definition: top_efex_processor.vhd:99
top_efex_processor.XML_SHA
XML_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA of the XMLs.
Definition: top_efex_processor.vhd:120
top_efex_processor.CON_VER
CON_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of the top folder, see TOP_SHA.
Definition: top_efex_processor.vhd:117
top_efex_processor.IPBUS_LIB_SHA
IPBUS_LIB_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA of the ipbus submodule.
Definition: top_efex_processor.vhd:146
Generated on Tue Nov 11 2025 09:44:32 for eFEX firmware by   doxygen 1.9.1