eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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slave_process_fpga.vhd
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1 
12 
13 library IEEE;
14 use IEEE.STD_LOGIC_1164.all;
15 library ipbus_lib;
16 use ipbus_lib.ipbus.all;
17 use ipbus_lib.all;
18 
19 use work.spi.all;
20 use work.ipbus_decode_efex_infrastructure.all;
22 entity slaves is
23  generic (FPGA_FLAVOUR : integer := 0;
24  reg48 : bit_vector(15 downto 0) := x"0000";
25  reg49 : bit_vector(15 downto 0) := x"0000");
26  port(
28  ipb_clk : in std_logic;
30  ipb_rst : in std_logic;
32  ipb_in : in ipb_wbus;
34  ipb_out : out ipb_rbus;
36  status : in std_logic_vector(31 downto 0);
37  ---! control register
38  control_reg : out std_logic_vector(31 downto 0);
40  TOB_BCN_sych_reg : out std_logic_vector(31 downto 0);
42  tob_delay_reg : out std_logic_vector(31 downto 0);
44  tob_delay_status : in std_logic_vector(31 downto 0) := (others => '0');
46  tob_bc_reg : out std_logic_vector(31 downto 0);
48  tob_bc_status : in std_logic_vector(31 downto 0) := (others => '0');
50  reconfig_reg : out std_logic_vector(31 downto 0);
52  bcmuxvalue_sych_reg: out std_logic_vector(31 downto 0);
54  ttc_orbit_length_reg : out std_logic_vector(31 downto 0);
56  flash_miso : in std_logic;
58  flash_le : out std_logic;
60  flash_clko : out std_logic;
62  flash_mosi : out std_logic;
63  VAUXP, VAUXN : in std_logic;
64  Vp, Vn : in std_logic
65  );
66 
67 end slaves;
69 architecture rtl of slaves is
70 
71 
72  signal ipbw : ipb_wbus_array(N_SLAVES-1 downto 0);
73  signal ipbr, ipbr_d : ipb_rbus_array(N_SLAVES-1 downto 0);
74  signal ctrl_pulse_reg : std_logic_vector(63 downto 0);
75  signal nc_0, nc_1, nc_2 : std_logic_vector(63 downto 0);
76 
77 
78  signal flash_spi_in : spi_mi;
79  signal flash_spi_out : spi_mo;
80 
81  signal tob_delay_default, tob_bc_default : std_logic_vector(31 downto 0);
82 
83 begin
84 
85 -- spi flash pin assignment
86  flash_spi_in.miso <= flash_miso;
87 
88  flash_mosi <= flash_spi_out.mosi;
89  flash_le <= flash_spi_out.le;
90  flash_clko <= flash_spi_out.clk;
91 
92 -- Default values for tob_delay_reg and tob_bc_reg (only meaningful when FPGA_FLAVOUR = 1 or 2...)
93 
94  tob_delay_default <= x"01131412" when FPGA_FLAVOUR = 1 else x"01120f10"; -- corresponding to 18,20,19 or 16,15,18
95  tob_bc_default <= x"07131412" when FPGA_FLAVOUR = 1 else x"071f101f";
96 
97  fabric : entity ipbus_lib.ipbus_fabric_sel
98  generic map(NSLV => N_SLAVES, --defined in ipbus_decode_fpga_proc_common_registers
99  SEL_WIDTH => ipbus_sel_width)
100  port map(
101  ipb_in => ipb_in,
102  ipb_out => ipb_out,
103  sel => ipbus_sel_efex_infrastructure (ipb_in.ipb_addr),
104  ipb_to_slaves => ipbw,
105  ipb_from_slaves => ipbr
106  );
107 
108 
109  module_control : entity ipbus_lib.ipbus_ctrlreg_v
110  generic map (
111  N_CTRL => 1, --number of control reg
112  N_STAT => 1) --number of status reg
113  port map (
114  clk => ipb_clk,
115  reset => ipb_rst,
116  ipbus_in => ipbw(N_SLV_MODULE_REG),
117  ipbus_out => ipbr(N_SLV_MODULE_REG),
118  d => (0 => status),
119  q(0) => (control_reg),
120 -- qmask => (others => '0'),
121  stb => open
122  );
123 
124  tob_synch : entity ipbus_lib.ipbus_ctrlreg_v
125  generic map (
126  N_CTRL => 1, --number of control reg
127  N_STAT => 0) --number of status reg
128  port map (
129  clk => ipb_clk,
130  reset => ipb_rst,
131  ipbus_in => ipbw(N_SLV_TOB_SYNCH),
132  ipbus_out => ipbr(N_SLV_TOB_SYNCH),
133  d => (others => (others => '0')),
134  q(0) => (TOB_BCN_sych_reg),
135 -- qmask => (others => '0'),
136  stb => open
137  );
138 
139 
140  xadc : entity work.ipbus_xadc_drp -- accessing and monitoring XADC
141 
142  generic map (
143  reg48 => reg48,
144  reg49 => reg49)
145  port map(
146  ipb_clk => ipb_clk,
147  reset => ipb_rst,
148  VAUXP => "00000" & VAUXP ,
149  VAUXN => "00000" & VAUXN ,
150  Vp => Vp,
151  Vn => Vn,
152  ipbus_in => ipbw(N_SLV_XADC),
153  ipbus_out => ipbr(N_SLV_XADC)
154 
155  );
156 
157  reconfig : entity ipbus_lib.ipbus_ctrlreg_v
158  generic map (
159  N_CTRL => 1, --number of control reg
160  N_STAT => 0) --number of status reg
161  port map (
162  clk => ipb_clk,
163  reset => ipb_rst,
164  ipbus_in => ipbw(N_SLV_RECONFIGURE),
165  ipbus_out => ipbr(N_SLV_RECONFIGURE),
166  d => (others => (others => '0')),
167  ctrl_default(0) => x"00020000",
168  q(0) => (reconfig_reg),
169  stb => open
170  );
171 
172  ttc_orbit_length : entity ipbus_lib.ipbus_ctrlreg_v
173  generic map (
174  N_CTRL => 1,
175  N_STAT => 0)
176  port map (
177  clk => ipb_clk,
178  reset => ipb_rst,
179  ipbus_in => ipbw(N_SLV_TTC_ORBIT_LENGTH),
180  ipbus_out => ipbr(N_SLV_TTC_ORBIT_LENGTH),
181  d => (others => (others => '0')),
182  q(0) => (ttc_orbit_length_reg),
183  stb => open
184 
185  );
186 
187 
188  bcmuxvalue_sync : entity ipbus_lib.ipbus_ctrlreg_v
189  generic map (
190  N_CTRL => 1,
191  N_STAT => 0)
192  port map (
193  clk => ipb_clk,
194  reset => ipb_rst,
195  ipbus_in => ipbw(N_SLV_BCMUXVALUE_SYNC),
196  ipbus_out => ipbr(N_SLV_BCMUXVALUE_SYNC),
197  d => (others => (others => '0')),
198  q(0) => (bcmuxvalue_sych_reg),
199  stb => open
200  );
201 
202  tob_bus_delay : entity ipbus_lib.ipbus_ctrlreg_v
203  generic map (
204  N_CTRL => 1, --number of control reg
205  N_STAT => 1) --number of status reg
206  port map (
207  clk => ipb_clk,
208  reset => ipb_rst,
209  ipbus_in => ipbw(N_SLV_TOB_DELAY),
210  ipbus_out => ipbr(N_SLV_TOB_DELAY),
211  d(0) => tob_delay_status,
212  q(0) => tob_delay_reg,
213  ctrl_default(0) => tob_delay_default,
214  stb => open
215  );
216 
217  tob_bc_delay : entity ipbus_lib.ipbus_ctrlreg_v
218  generic map (
219  N_CTRL => 1, --number of control reg
220  N_STAT => 1) --number of status reg
221  port map (
222  clk => ipb_clk,
223  reset => ipb_rst,
224  ipbus_in => ipbw(N_SLV_TOB_BC_DELAY),
225  ipbus_out => ipbr(N_SLV_TOB_BC_DELAY),
226  d(0) => tob_bc_status,
227  q(0) => tob_bc_reg,
228  ctrl_default(0) => tob_bc_default,
229  stb => open
230  );
231 
232  spi_flash : entity work.ipbus_spi32 -- spi controller
233  generic map(
234  BYTE_SPI => true,
235  ADDR_WIDTH => 9
236  )
237  port map(
238  ipbus_clk => ipb_clk,
239  reset => ipb_rst,
240  ipb_in => ipbw(N_SLV_FLASH_SPI_RAM),
241  ipb_out => ipbr(N_SLV_FLASH_SPI_RAM),
242  spi_in => flash_spi_in,
243  spi_out => flash_spi_out,
244  selreg => open --flash_select
245 
246  );
247 
248  RAM : entity ipbus_lib.ipbus_ram -- internal ram for testing the iPbus transactions.
249  generic map(
250  ADDR_WIDTH => 10
251  )
252  port map(
253  clk => ipb_clk,
254  reset => ipb_rst,
255  ipbus_in => ipbw(N_SLV_RAM),
256  ipbus_out => ipbr(N_SLV_RAM)
257  );
258 
259 end rtl;
ipbus_decode_efex_infrastructure
Definition: ipbus_decode_efex_infrastructure.vhd:14
ipbus_spi32
ipbus_spi32
Definition: ipbus_spi32.vhd:17
ipbus_spi32.reset
in reset std_logic
reset
Definition: ipbus_spi32.vhd:28
ipbus_spi32.spi_in
in spi_in spi_mi
spi input signals
Definition: ipbus_spi32.vhd:34
ipbus_spi32.selreg
out selreg std_logic_vector( 1 downto 0)
select output
Definition: ipbus_spi32.vhd:39
ipbus_spi32.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: ipbus_spi32.vhd:32
ipbus_spi32.spi_out
out spi_out spi_mo
spi output signals
Definition: ipbus_spi32.vhd:36
ipbus_spi32.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: ipbus_spi32.vhd:30
ipbus_spi32.ipbus_clk
in ipbus_clk std_logic
ipbus clk of 31.25MHz
Definition: ipbus_spi32.vhd:26
ipbus_xadc_drp
Definition: ipbus_xadc_drp.vhd:30
slaves.rtl
process fpga common slaves
Definition: slave_process_fpga.vhd:69
slaves
process fpga common slaves
Definition: slave_process_fpga.vhd:22
slaves.tob_delay_reg
out tob_delay_reg std_logic_vector( 31 downto 0)
TOB delay register.
Definition: slave_process_fpga.vhd:42
slaves.ipb_rst
in ipb_rst std_logic
IPBus Reset input.
Definition: slave_process_fpga.vhd:30
slaves.flash_le
out flash_le std_logic
chip select
Definition: slave_process_fpga.vhd:58
slaves.tob_delay_status
in tob_delay_status std_logic_vector( 31 downto 0) :=( others => '0')
TOB delay status register.
Definition: slave_process_fpga.vhd:44
slaves.flash_miso
in flash_miso std_logic
serial input of the spi flash
Definition: slave_process_fpga.vhd:56
slaves.status
in status std_logic_vector( 31 downto 0)
ststus register
Definition: slave_process_fpga.vhd:36
slaves.tob_bc_status
in tob_bc_status std_logic_vector( 31 downto 0) :=( others => '0')
TOB BC delay stataus register.
Definition: slave_process_fpga.vhd:48
slaves.ttc_orbit_length_reg
out ttc_orbit_length_reg std_logic_vector( 31 downto 0)
ttc orbit length
Definition: slave_process_fpga.vhd:54
slaves.ipb_clk
in ipb_clk std_logic
IPBus clock.
Definition: slave_process_fpga.vhd:28
slaves.flash_clko
out flash_clko std_logic
flash clock
Definition: slave_process_fpga.vhd:60
slaves.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: slave_process_fpga.vhd:34
slaves.flash_mosi
out flash_mosi std_logic
serial out of the spi flash
Definition: slave_process_fpga.vhd:62
slaves.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: slave_process_fpga.vhd:32
slaves.tob_bc_reg
out tob_bc_reg std_logic_vector( 31 downto 0)
TOB BC delay register.
Definition: slave_process_fpga.vhd:46
slaves.reconfig_reg
out reconfig_reg std_logic_vector( 31 downto 0)
reconfigure address register
Definition: slave_process_fpga.vhd:50
slaves.TOB_BCN_sych_reg
out TOB_BCN_sych_reg std_logic_vector( 31 downto 0)
TOB_BCN_sych regsiter.
Definition: slave_process_fpga.vhd:40
slaves.bcmuxvalue_sych_reg
out bcmuxvalue_sych_reg std_logic_vector( 31 downto 0)
bc mux value sync
Definition: slave_process_fpga.vhd:52
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