slaves Entity Reference

process fpga common slaves More...

Inheritance diagram for slaves:

Entities
rtl	architecture
	process fpga common slaves More...

Libraries
IEEE
ipbus_lib

Use Clauses
STD_LOGIC_1164
ipbus
all
spi	Package <spi>
ipbus_decode_efex_infrastructure	Package <ipbus_decode_efex_infrastructure>

Generics
FPGA_FLAVOUR	integer := 0
reg48	bit_vector ( 15 downto 0 ) := x " 0000 "
reg49	bit_vector ( 15 downto 0 ) := x " 0000 "

Ports
ipb_clk	in	std_logic
		IPBus clock.
ipb_rst	in	std_logic
		IPBus Reset input.
ipb_in	in	ipb_wbus
		IPBus input bus going from master to slaves.
ipb_out	out	ipb_rbus
		IPBus output bus going from slaves to master.
status	in	std_logic_vector ( 31 downto 0 )
		ststus register
control_reg	out	std_logic_vector ( 31 downto 0 )
TOB_BCN_sych_reg	out	std_logic_vector ( 31 downto 0 )
		TOB_BCN_sych regsiter.
tob_delay_reg	out	std_logic_vector ( 31 downto 0 )
		TOB delay register.
tob_delay_status	in	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
		TOB delay status register.
tob_bc_reg	out	std_logic_vector ( 31 downto 0 )
		TOB BC delay register.
tob_bc_status	in	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
		TOB BC delay stataus register.
reconfig_reg	out	std_logic_vector ( 31 downto 0 )
		reconfigure address register
bcmuxvalue_sych_reg	out	std_logic_vector ( 31 downto 0 )
		bc mux value sync
ttc_orbit_length_reg	out	std_logic_vector ( 31 downto 0 )
		ttc orbit length
flash_miso	in	std_logic
		serial input of the spi flash
flash_le	out	std_logic
		chip select
flash_clko	out	std_logic
		flash clock
flash_mosi	out	std_logic
		serial out of the spi flash
VAUXP	in	std_logic
VAUXN	in	std_logic
Vp	in	std_logic
Vn	in	std_logic

Detailed Description

process fpga common slaves

This slave process_fpga comprises a collection of IPBus slaves of the process FPGAs a slave being an interface between IPBus and the application logic It implements a simple control or status register, an area of RAM that is mapped to IPBus, a stare machine under IPBus control, or an interface to a second bus, such as SPI and XADC. The ipbus bus fabric, address select logic, data multiplexers This version selects the addressed slave depending on the state of incoming control lines

Author

Mohammed Siyad

Definition at line 22 of file slave_process_fpga.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Process_Common_slave/slave_process_fpga.vhd